IBM unveils sub-1 nanometer chip with new 3D transistor design

IBM (NYSE: IBM) announced on June 25, 2026, the development of a sub-1 nanometer chip technology, featuring a transistor architecture at the 0.7 nanometer, or 7 angstrom, node. The company claims this is the first chip technology to operate below the 1 nanometer threshold.

The new chip uses what IBM calls a "nanostack" architecture, a three-dimensional design that vertically stacks and staggers transistors. IBM states the chip packs nearly 100 billion transistors onto a fingernail-sized chip, approximately twice the density of IBM's 2 nm chip unveiled in 2021.

According to published technical results, the chip is projected to deliver up to 50% more performance or 70% greater energy efficiency compared to IBM's 2 nm node chips. IBM also presented research at VLSI 2026 showing the nanostack architecture provides 40% scaling in SRAM.

"With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," said Jay Gambetta, Director of IBM Research and IBM Fellow.

IBM's nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering demonstration, and functional CMOS inverter operation. IBM said its semiconductor roadmap projects at least a decade of future scaling from the new architecture.

IBM conducts this research at a semiconductor facility in Albany, New York, in partnership with Lam Research Corp., Tokyo Electron, and SCREEN Semiconductor Solutions. The facility is set to receive a High Numerical Aperture Extreme Ultraviolet lithography tool developed by ASML.

IBM indicated it sees a path to production of nanostack technology within approximately five years. The company also recently announced plans to form Anderon, described as a standalone IBM company intended to serve as a quantum foundry.

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