SealSQ to show two quantum-resistant chips and ASIC concept at electronica 2026

SealSQ Corp (NASDAQ: LAES) announced it will exhibit at electronica 2026, scheduled for November 10–13 at Trade Fair Center Messe Munich in Germany, where the company plans to unveil two new quantum-resistant chips and a post-quantum application-specific integrated circuit design concept.

SealSQ, along with its subsidiary IC'Alps, will occupy Hall C6, Booth 670. The company will present three products targeting the post-quantum security market:

The VaultIC409 is a quantum-ready secure element built on the QS7001 platform, currently undergoing Common Criteria EAL5+ certification. It supports ML-KEM and ML-DSA algorithms alongside classical cryptography. Engineering samples are planned for the second quarter of 2027.

The QVault TPM is a post-quantum Trusted Platform Module that generates and stores ML-DSA and ML-KEM keys on-chip alongside RSA and ECC. It is on a certification path covering FIPS 140-3 and Trusted Computing Group standards. wolfSSL has added wolfTPM support for QVault.

QASIC is a post-quantum ASIC design offering developed by IC'Alps, SealSQ's Grenoble and Toulouse-based subsidiary, targeting manufacturers that require quantum-resistant security built into a custom chip.

The booth will feature live demonstrations across automotive, medical, smart energy, smart home, and access-control applications. A quantum-computer mock-up from Quobly, SealSQ's silicon quantum-computing partner, will also be on display.

On November 11, SealSQ will join NXP and Infineon for a roundtable titled "Physical AI at the Edge for Industrial Security" at the IIoT Forum. On November 13, the company will deliver a keynote at the Embedded Systems World Forum on embedding certified secure hardware for post-quantum security migration.

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