Intel reveals GPU D-series specs and new Xeon rack designs at OCP

Intel (Nasdaq: INTC) disclosed technical specifications for its GPU D-series, formerly code-named Crescent Island, and introduced new Xeon-based rack designs at the Open Compute Project Global Summit, according to a company statement.

The Intel GPU D-series is built on Intel's Xe3P architecture and features up to 480 GB of LPDDR5X memory, 1.5 TB/s of memory bandwidth and 1.3 petaflops of FP8 compute within a 350-watt power envelope. Intel noted that its own branded PCIe card carries 160 GB of LPDDR5X memory, with partner-built ODM cards able to reach up to 480 GB. The card supports models with up to 300 billion parameters on a single card and more than one trillion parameters in an eight-GPU configuration. The standard PCIe form factor uses air cooling, allowing deployment in existing data center environments. Customer sampling is underway.

On the CPU side, select Xeon 6+ rack configurations scale beyond 46,000 cores per rack at 133.45 kW total rack power. The new rack designs are being developed with ecosystem partners and leverage the Open Compute Project's Open Rack v3 standard.

Intel also highlighted software efforts, including day-zero support for Meta's Muse Glimmer model across the GPU D-series and Xeon processors. The company's AI for Enterprise Agent Toolkit is available on Xeon processors, with plans to extend support to Intel GPUs.

On the open infrastructure side, Intel said it has made 116 contributions to the Open Compute Project since 2011. At the summit, the company showcased a contribution to the Open Adapter Card workgroup, an effort with industry partners to define a standardized sub-rack accelerator card form factor aimed at improving mechanical, electrical and management interoperability.

"Agentic AI is changing what customers need from their data centers," said Kevork Kechichian, executive vice president and general manager, Data Center Group, Intel. "Success will depend not on any single component, but on open, heterogeneous infrastructure that brings together Xeon, purpose-built acceleration and interoperable software."

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