GlobalFoundries unveils FD-SOI chip platform planned for 2028

GlobalFoundries (Nasdaq: GFS) announced plans for a new semiconductor platform called FDX Fusion, an FD-SOI technology designed for edge computing and physical AI applications, with manufacturing set to begin in 2028 at its facility in Dresden, Germany.

According to a company statement, the first generation of FDX Fusion is expected to deliver seven nanometer class digital performance and more than 2x density improvement over the company's first-generation FDX technology. The platform is said to offer RF performance up to 0.5 THz, along with analog, mixed-signal, embedded non-volatile memory and in-memory computing capabilities.

GlobalFoundries said demonstrator silicon is targeted for early customer evaluation in early 2027, with an initial process design kit release planned for mid-2027. Volume manufacturing is planned for 2028.

The company said it is engaged with several customers on early development and evaluation. Bosch, Infineon, NXP, Siemens, Tesla and CEA-Leti each provided statements in support of the platform. Infineon's Executive Vice President of External Wafer Manufacturing Patrick Press said the two companies are "strengthening their collaboration to define and explore future 7nm class FDX Fusion technologies for next generation radar and wireless communication products."

Tesla's Vice President of Supply Chain Karn Budhiraj said that "GF's technology roadmap reflects the type of semiconductor investment needed to bring physical AI to the masses."

GlobalFoundries said the Dresden facility is expanding under the framework of the European Chips Act to increase capacity for semiconductor solutions across security and defense, industrial, and connectivity applications.

The FDX Fusion platform is intended to address automotive, consumer, and industrial markets, including robotics, autonomous systems, sensor-fusion architectures, and intelligent connected devices. The company said customers will be able to access design enablement tools including MIPS and ARC processor IP, and RISC-V instruction set architecture support optimized for the platform.

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