D-Wave publishes quantum error correction research in Nature

D-Wave Quantum Inc. (Nasdaq: QBTS) announced research published in the peer-reviewed journal Nature that the company says advances fault-tolerant gate-model quantum computing through its superconducting dual-rail qubit architecture.

The paper, titled "An entangling gate for dual-rail erasure qubits," details a two-qubit entangling gate achieving approximately 99.9% fidelity with gate times of about 500 nanoseconds. According to D-Wave, the design preserves hardware-level error detection during two-qubit operations, which the company says reduces the physical qubit overhead typically required for quantum error correction.

D-Wave simulations cited in the research indicate the dual-rail architecture could reduce the logical error rate by a factor of 10 for each increment in error correction capability, a metric the company refers to as Lambda.

"Superconducting quantum computers are known for speed, but achieving the high fidelity needed for scalable, fault-tolerant systems has remained a challenge," said Dr. Alan Baratz, CEO of D-Wave. "This research demonstrates that our dual-rail architecture combines fast superconducting operations with high-fidelity performance while preserving native hardware-level error detection."

Dr. Robert Schoelkopf, chief scientist at D-Wave, noted that the entangling gate described in the paper is already integrated into the company's existing gate-model systems.

The findings support D-Wave's previously announced gate-model development roadmap, which targets completion of a 100-logical-qubit system capable of performing more than one million operations by 2032. The roadmap combines the dual-rail architecture with integrated cryogenic control technology.

D-Wave describes itself as offering both annealing and gate-model quantum computing systems. The company is headquartered in Palo Alto, California.

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