Synopsys launches new chip verification platforms for AI designs

Synopsys Inc. (NASDAQ: SNPS) announced new hardware-assisted verification platforms and capabilities designed to support AI chip development from data centers to edge devices. The company introduced software-defined approaches that deliver up to 2x performance improvements and capacity scaling for its ZeBu Server 5 platform.

The new product lineup includes HAPS-200 12 FPGA and ZeBu-200 12 FPGA platforms for mainstream designs, featuring EP-Ready Hardware that extends emulation and prototyping capacity by 2x compared to previous 6 FPGA systems. These platforms utilize AMD Versal Premium VP1902 adaptive SoCs and offer configurability between prototyping and emulation modes.

Synopsys also released the HAPS-200 1 FPGA platform as a desktop system for IP verification and software development. The new platforms include hardware-assisted test automation capabilities for detecting cache-coherency and subsystem-level issues.

"Hardware-assisted verification is no longer optional. It is critical to meeting aggressive time-to-market goals and ensuring silicon readiness," said Salil Raje, Senior Vice President and General Manager of AMD's Adaptive and Embedded Computing Group.

The company introduced Real-Number Models emulation for mixed-signal and system-level designs, enabling abstraction of analog behavior within digital verification workflows. New fault emulation capabilities support scalable fault injection and analysis across RTL simulation, emulation, and prototyping.

Software-defined enhancements are available immediately across the hardware-assisted verification portfolio. The HAPS-200 12 FPGA platform is available now, while the ZeBu-200 12 FPGA platform will be available in Q3 2026. The HAPS-200 1 FPGA platform is currently available.

The announcements were made at the Synopsys Converge conference taking place March 11-12 at the Santa Clara Convention Center.

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