Form 6-K ASML HOLDING NV For: Sep 30

Exhibit 99.1

Small Talk 2021 investor Day virtual
1

Opening Investor Day
Skip Miller
Vice President Investor Relations

Question & Answer session
Slide 3
29 Sept. 2021 Public 3

Investor Day 2021 survey
Slide 4
29 Sept. 20211
PUBLIC

Agenda    
Presentations    
13:00    - 13:05Opening remarksSkip Miller
13:05    - 13:35Company Strategy and Shareholder ValuePeter Wennink
13:35    - 14:05Industry Roadmap and Technology StrategyMartin van den Brink
14:05    - 14:35EUV Products and Business OpportunityChristophe Fouquet
14:35    - 14:45Break
14:45    - 15:15Applications Products and Business OpportunityJim Koonmen
15:15    - 15:45DUV Products and Business OpportunityRon Kool
15:45    - 16:15Installed Base Business OpportunityWayne Allan
16:15    - 16:25Break
16:25    - 16:55ASML Business Model and Capital Allocation StrategyRoger Dassen
16:55    - 17:05Closing remarksPeter Wennink
17:05    - 17:15Break
17:15    - 18.00Q&A sessionAll
All times CET    
Slide 5
29 Sept. 2021

Forward Looking Statements
Slide 6
29 Sept. 2021
This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy, dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”, “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets, as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets, changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for, and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of this report or to conform such statements to actual results or revised expectations, except as required by law.
Public

ASML SMALL TALK 2021 INVESTOR DAY VIRTUAL 7

Exhibit 99.2

Market drivers, company strategy and creating sustainable value
Peter Wennink
President and
Chief Executive Officer

Industry megatrends are fueling market growth into the future
• Global megatrends in the electronics industry, supported by a highly profitable and fiercely innovative ecosystem, are expected to continue to fuel growth across the semiconductor market
• Countries push for technological sovereignty will drive increased capital intensity
• Translating to increased wafer demand at both advanced and mature nodes.
Enabling ASML’s strong growth opportunity into the next decade
• Investments in wafer capacity, with increasing lithography intensity, fuel the strong growth of our business as we transition to an increased mix of EUV
• ASML and our supply chain partners are actively adding capacity to meet future customer demand
Our strategy aims to deliver long-term growth and stakeholder value
• With strong demand for our products and execution of our strategic priorities, we have increased confidence in our long-term growth opportunities while continuing to deliver value to our stakeholders
• Our ESG Sustainability Strategy builds on achieved performance improvements and details how we contribute to a digital and sustainable future, in close collaboration with our partners

End-market demand
Lithography market Strategy
Sustainability

Global    megatrends shaping the connected world
Slide 4
29 Sept. 2021
5G    AI
Cloud    5G & ArtificialIntelligentGaming, simulation
infrastructure    intelligence edge& visualization
Sources: Intel, “Engineering the future”, March 23, 2021 / NVIDIA, Investor Day 2021 / AMD, Corporate Presentation 2021    Public

The future will be all    about distributed computing
Slide 5
29 Sept. 2021
Public
network
Bringing the cloud closer    
to devices at the edge    
Privacy
Performance
Personalization
Cloud    Edge cloud On device
Private
networks
Source: Ziad Asghar, Qualcomm, “Qualcomm AI leading the way with distributed intelligence, Embedded vison summit, Sept 2020     Public

The world’s transition to 5G is just starting    
Lower latency, higher bandwidth will enable a connected world    Slide 6
29 Sept. 2021
(human-to-machine and machine-to-machine)    
10     250
)By 2026, global 5G
9     $
subscriptions are
(billion)    8 200(billionestimated to top 3.5
7     5Gbillion with
infrastructure
6     150
technology     spendinginvestment of $150B
by    5 4G
By 2030, that
4     100infrastructureinvestment is expected
subscriptions    3 3G5Gto grow to $250B
2     50This transformation
2G has only just begun
Mobile    1 Cumulative
0     0
2015    2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026
Sources: Ericsson Mobility Report, June 2021; Nokia CMD2021     Public

The electronics industry just keeps going
Slide 7
29 Sept. 2021
There are an estimated 40 billion    
connected devices in use today    
Roughly 5 for every person on the planet (7.8 billion people)
In ten years, this number    
is expected to grow to    350 billion
That’s 41 per person (assuming population growth to 8.5 billion)
…generating huge amounts of data:    175 zettabytes
(that’s 175,000,000,000,000,000,000,000 bytes) by 2025
Source: International Data Corporation (IDC)     Public
7

ASML operates in an industry value chain that has considerable    
means, with strong incentives to compete and drive innovation    Slide 8
29 Sept. 2021
50 top technology companies in our ecosystem generated $493 billion of EBIT in 2020    
ASML     AMATLAMTELKLA
4.8     4.63.42.61.7Semi Equipment
19.2     23.75.94.3 3.4 1.7 1.31.20.7 Semi
Manufacturers
7.8    5.1 4.5 1.5 1.4 0.930.6DevicesASML
SemiPeers
AnalogDesignSemi
Non-Semi
12.53.8 3.9 3.42.8 2.7 2.3 2.2 1.9 1.11.21.0
74.3     Hardware
5.95.1 3.16.2
In our ecosystem, EBIT
has grown at an annual
rate of more than 10%
since 2016
60.2     41.232.725.522.915.214.6 7.63.32.4 2.12.1Total EBIT, US$ Billion
Software
& Service+14%
®
493
443 400
371+23%
295
2016 1718 19 2020
Source: Bloomberg (GICS 45 classification); companies’ annual reports, and ASML analysis     Public
8

Countries push for “technological sovereignty”
Slide 9
29 Sept. 2021
Biden doubles down on a $50 billion plan to invest in chips
Fortune (April 2021)
EU aims to be independent chip power with 20% global share
Nikkei (March 2021)
South Korea joins global chipmaking race with $450 billion spending plan
Fortune (May 2021)
Japan lays out National Project for chips after lost decades
Bloomberg (June 2021)
China wants to boost disruptive semiconductor technologies
Shanghai Daily (May 2021)
9

Government funding may boost investments    
Beyond industry CapEx of $150B per year, which may lead to cyclicality    Slide 10
29 Sept. 2021
$52B     $15B$80B
US chipmaking and R&D    EU Industrial Alliance on Microelectronics China National IC Industry Investment
Incentives for semiconductor manufacturing    Combined public and private investment $24-$35B. Fund II ($35B)
National Semiconductor Technology Center    Goal: rebuild Europe’s capacity to produce high- Provincial Funds ($45B)
Goal: regain global leadership position on    quality microelectronics. Goal: China makes 70% of the chips it uses by
advanced chip manufacturing     2025
The industry continues to underestimateJapan Ministry of Economy, Trade &
end market demand and therefore we    Industry (METI) $1.8B government fund for $2.2B
advanced semiconductors and $0.4B funding for
would like to have additional capacity    advanced chipmaking technology.
The additional infrastructure created from
this spending will be managed rationally    ‘Korean Semiconductor Belt’
by a few very large manufacturers    Loans for increasing 8-inch foundry capacity $0.8B
and investments in materials, components,
equipment and packaging.
Source: IC Insights, European Commission, Technode, ASML Government Affairs team    
10

Semi end markets expected to grow 7% longer-term    
Slide 11
Smartphone (B$)    Consumer electronics (B$) Personal computing (B$)29 Sept. 2021
+6.7%+2.6%
210+7.8%
116    161 155 98100119 110132
115    144 155 16069102 120109 113
108    106 486466 67 7083 78 93 86
76 87     36 35 43 43 48
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30    15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Wired & wireless infrastructure (B$)    Servers, datacenters & storage (B$) Total Semiconductor, B$ 187Forecast +5.9%+8.0%941 4763110112 37     44 4749 518176 9297 99+7.4%
32 30 31    36 38 6361
42 42 627 626 667 571605 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30    15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
476 466 Automotive (B$)    Industrial electronics (B$) 422 422 335 341 +15.7% 131+10.2%119 73 806575 81
42     50 58 645250 5867
30 34 39    41 39 37 35 4650
CAGR
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30    15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 302020-2025
Source: ’19-’25: Gartner 2Q21 Forecast (Jun30, 2021); 2030: ASML extrapolation of data to 2030 using ’15-’25 Compound Annual Growth Rate (CAGR)     Public
11

Translating to growth of wafer demand in    all segments
Slide 12
29 Sept. 2021
2015 20202025CAGR
1.. 7
1.1+9.9%
Logic & MPU    
(£ 28 nm)    0.5
1.8
1.2 1.4+5.2%
DRAM    
2.1
1.5 1.6+5.7%
NAND    
million wafer starts/month
PCs and laptops    Smartphones and tablets ServersAutomotiveConsumer incl. wearablesOther
Source: Gartner device units 2017-2022; ASML model extrapolated through 2025     Public
12

Advanced and mature nodes drive investments in wafer capacity:    
~500k wafers/month per year 2020—2025, CAGR >5%     Slide 13
29 Sept. 2021
140     • Growing wafer capacity across
equiv    120 NANDall market segments drives
NANDincreased litho demand
300mm    100 DRAM
yr)     DRAM• Mature nodes (³40nm) continue
fer/    80 to grow in both 200mm and
wa     Adv Logic 300mm
60    
(million     MatureMarketGrowth ‘20-’25CAGR ’20-’25
40     NAND+100 kwspm/y 5.7%
MatureDRAM+80 kwspm/y 5.2%
Capacity    20 Adv Logic +125 kwspm/y 9.9%
Mature+200 kwspm/y 3.9%
0    
2010    2015 20202025Total+505 kwspm/y 5.2%
kwspm/y = x1000 wafer starts per month per year
Source: ASML analysis, Adv Logic = Advanced Logic £28nm     Public
13

End-market demand
• Lithography market
Strategy
Sustainability
14

Litho market expected to see continued strong growth    
Market size value worldwide revised upwards     Slide 15
29 Sept. 2021
Original (2018) CAGR     Revised (2021)
CAGR
1997-2010    2010-2017 2017-2025E2017-2025E
Semi end markets
Expected to show
6.2%    4.9% 4.9%above average growth5.4%
Semi CapEx
WFE market growing faster to build
capacity to fulfill strong(er) future end
4.6%    7.4% 3.5%market demand5.9%
Lithography CapEx
Lithography to outgrow13.8%
6.6%     7.5%overall WFE market
3.4%    
Single    Multi EUV
patterning    patterning
Source: 2018 Analyst Day; Semi-WSTS.org/Gartner, CapEx-Gartner, Litho: SEMI.org/VLSI     Public
15

Capital intensity* outlook supports strong semi growth    
and lithography intensity increasing over time     Slide 16
29 Sept. 2021
CapEx to support period of strong semi growth    Litho growth faster than total WFE
35%     30%
Litho/WFE Equipment
30%    
25%
25%    
Other20%
22%
intensity 20%     CapEx equipment
15%     Packageof 15%
Capital     /test%
10%     as 10%
Litho    2015 20202025Non-litho
intensity    1.7% 3.0%3.7%WFELitho
5%    
5%
Litho
0%    
1997 2001 2005 2009    2013 2017 202120250%
19972001 200520092013201720212025
*Capital intensity = CapEx/Semi Revenue.    | Sources: Gartner, WSTS.org, SEMI.org VLSI Public
16

EUV increasing contribution of net system sales    
Slide 17
29 Sept. 2021
2020    2025 estimate
Metrology &    
Inspection    
Metrology &    Dry
Inspection    
Dry    
EUV    ArFi
ArFi    EUV
Pie size reflects expected revenue growth    
Source: ASML analysis     Public
17

2025 growth scenarios supported by expansion of    
capacity and productivity increase of our systems    Slide 18
29 Sept. 2021
DUV capacity growth 2020—2025    EUV capacity growth 2020—2025
Number of units    Number of units
~1.5x    >2x
Wafer capacity*    Wafer capacity*
~2x    >3x
Note: excluding refurbished systems & field upgrades    Note: excluding capacity for 0.55 EUV
Driver    Goal
Build faster    Drive cycle time reduction >35% (EUV); >10% (DUV)
More people/tooling    20% growth in people to support 2025 operations
Increase production space    Increase production space 25% (EUV / DUV)
Increase productivity of machines    Productivity improvements 25%-60%
*Wafer capacity=units x productivity     Public
18

Semiconductor and equipment demand provide    growth
opportunity into the next decade     Slide 19
29 Sept. 2021
Semiconductors versus wafer fab equipment
1200     160
Semiconductors
1000     140
B)     Wafer Fab Equipment120 B)
$    800 $
(     100 (
sales    600 80 sales
400     60
Semi     40 WFE
200     20
0     0
2000    2005 2010 2015202020252030
Source: VSLI Research- Sept 2021     Public
19

End-market demand Lithography market
• Strategy
Sustainability
20

Execution on our strategic priorities since    2018
Slide 21
29 Sept. 2021
Original ASML strategy (2018) Progress
Strengthen Litho+ leadership with in-device metrology •Delivered YieldStar 1375 and 1385 in-device
Holistic Litho     enabling correction of process induced overlaymetrology and eP5 e-beam metrology solutions
extension    • Build a leading position in Pattern Fidelity Control leveragingto extend overlay and EPE control
e-beam metrology and inspection combined with superior litho •Delivered eScan1000, the first multi-beam
and fast stages e-beam inspection system
Drive DUV performance•NXT:2000 and 2050i in volume manufacturing
DUV     •Continue to lead in innovation•Dry to NXT Platform (ArF)
performance     •Drive operational cost down and improve uptime
• Expand installed base business
Deliver on high volume manufacturing, service and•Accelerated EUV roadmap, NXE:3400C and
EUV     financial performanceNXE:3600D insertion in Logic and DRAM HVM
industrialization    • Enhance EUV value for future nodes by extending NA 0.33•Service model in place and generating revenue
product portfolio down to the 3nm Logic node
Enable High-NA EUV at 3nm Logic node, followed by Memory•High-NA facilities in place and modules
nodes at comparable density underway
High-NA    
Public
21

ASML’s strategic priorities moving forward    
Slide 22
29 Sept. 2021
Refreshed ASML Strategy (2021) Plans
Strengthen    • Enhance execution capabilities to meet customers’ needs•Deliver cost, performance and robustness to
customer     while delivering on our commitment to sustainabilitymeet customer needs
trust     •Expand our ESG strategy around nine themes to
further drive sustainability
Holistic Litho    • Build a leading position in Edge Placement Error•Combine YieldStar and eP5 e-beam metrology
and     with solutions to extend overlay and EPE monitor
applications     and control
•Extend multibeam e-beam productivity for HVM
Drive DUV performance and market share•Extend immersion capability
DUV     •Dry to NXT platform (KrF)
performance    
EUV    • EUV high volume production performance, ramp and support•Execute EUV roadmap (3600D, 3800E, 4000F)
industrialization     •Drive good wafers out: productivity increase and
availability improvements
Enable litho simplification for future nodes •Drive commonality across EUV platforms
High-NA     •High-NA (0.55 EUV) ready for HVM in
2025Public
22

End-market demand Lithography market Strategy
• Sustainability
23

How we contribute to a digital, sustainable future
Slide 24
29 Sept. 2021
Our Purpose Digital technology helps society book social progress Unlocking the potential of people and society by and can help cut global emissions by 15% in 2030 pushing technology to the new limits.
Our Vision We develop lithography technology to continue to We enable groundbreaking technology to solve some produce microchips that are three times of humanity’s toughest challenges. more energy-efficient every two years
Our Mission
Together with our partners, we provide leading We help our customers minimize materials and patterning solutions that drive the advancement of energy required to produce advanced microchips microchips.
Our Values We drive a roadmap towards zero waste by 2030, We Challenge, Collaborate and Care. net zero value chain emissions by 2040, with a diverse and engaged group of world-class talents and partners
24
Public

Our ESG Sustainability strategy    focuses on 9 themes
For long-term stakeholder value creation and contribution to UN SDGs*    Slide 25
29 Sept. 2021
Environment    1. Energy Efficiency 2. Circular
& Climate Action     Economy
3. Attractive     6. Valued
4. Innovation    5. Responsible
Social    Workplace for Partner for Our
Ecosystem    Supply Chain
All     Communities
Governance    7. Integrated 8. Stakeholder9. Transparent
Governance    Engagement Reporting
* United Nations Sustainable Development Goals     Public
25

ASML commits to achieve net zero emissions by    2040
in close collaboration with our suppliers and customers     Slide 26
29 Sept. 2021
Category    Improvement
2020 emissions    lever 20202025203020402050
2    
&    
1    Manufacturing & â–ªReduce energyNet
â–ªUse green energy
Scope    buildings â–ªCompensate emissionszero
0.015 Mt CO2e    
Continue to drive energy efficiency & renewable energy
Business travel    â–ª Reduce energyNet
â–ªUse green energy
& commuting    â–ª Compensate emissionszero
<0.1 Mt CO2e*     Global aim for
net zero by 2050
3    
Sourcing &    Supply chain collaboration on Net
z
Scope    supply chain roadmap towards net zero emissionsero
~3 Mt CO2e     Continue collaboration on Net Zero activities Net Product use    Semiconductor Industry collaboration on roadmap towards net zero emissions zero ~5 Mt CO2e**     *Business Travel & Commuting exceptionally low in 2020 due to COVID-19. 2019 emissions: 0.21 Mt CO2 equivalent     **Product use emissions is based on lifetime emissions (20 years) for systems sold in 2020 – in line with GHG protocol     Public
26

Rating agencies value ASML’s    ESG performance
Slide 27
29 Sept. 2021
Bottom     Top
(DJSI)    0 100
81
0     100
84
CCC     AAA
AAA
High     Low
risk     1risk
F     A
C
Source: Latest available scores (2020 or 2021) from respective rating agencies     Public
27

Industry megatrends are fueling market growth into the future
• Global megatrends in the electronics industry, supported by a highly profitable and fiercely innovative ecosystem, are expected to continue to fuel growth across the semiconductor market
• Countries push for technological sovereignty will drive increased capital intensity
• Translating to increased wafer demand at both advanced and mature nodes.
Enabling ASML’s strong growth opportunity into the next decade
• Investments in wafer capacity, with increasing lithography intensity, fuel the strong growth of our business as we transition to an increased mix of EUV
• ASML and our supply chain partners are actively adding capacity to meet future customer demand
Our strategy aims to deliver long-term growth and stakeholder value
• With strong demand for our products and execution of our strategic priorities, we have increased confidence in our long-term growth opportunities while continuing to deliver value to our stakeholders
• Our ESG Sustainability Strategy builds on achieved performance improvements and details how we contribute to a digital and sustainable future, in close collaboration with our partners
28

Forward Looking Statements
Slide 29
29 Sept. 2021
This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy, dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”, “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets, as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets, changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for, and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of this report or to conform such statements to actual results or revised expectations, except as required by law.
Public
29

ASML SMALL TALK 2021 30

Exhibit 99.3

Technology Strategy to Drive
Moore’s Law into
Next Decade
Martin van den Brink
President and
Chief Technology Officer

Technology strategy    
Holistic Lithography roadmap is driven by our unique
Key messages     patterning control solutions that deliver customer value viaSlide 2
29 Sept. 2021
improved on product performance.
• Moore’s Law is alive and well! Industry innovation    • ASML’s comprehensive product portfolio is aligned to our
continues, fueled by system scaling, delivering highly valued     customers’ roadmaps, delivering cost effective solutions in support
semiconductor products.     of all applications from leading edge to mature nodes
• Semiconductor system scaling enables exponential    • Our next generation EUV technology, High-NA, is progressing
performance improvement and energy reduction in support of     well and will be the engine to drive the lithography roadmap into
significant growth of data exchange.     the next decade
• Customers’ roadmaps require continued shrink and    • Continued execution of our strategic priorities is expected to
reduction in edge placement error to drive affordable scaling     provide cost effective solutions for our customers, enable the
into next decade.     extension of the industry roadmap into the next decade, and
support our long-term sustainability commitment
2

• Moore’s Law evolution and customer roadmap
ASML’s strategic priorities
3

Significant device innovation in logic ahead of us    
scaling roadmap continues to 1 nm and beyond     Slide 4
29 Sept. 2021
3 nm     2 nm1,5 nm1 nm and beyond
PP: 44-48, MP: 21-24     PP: 40-44, MP: 18-21PP: 40-44, MP: 18-21PP: 38-42, MP: 15-18
BPR    BPR
FinFET    Nanosheets, BPR Forksheets, VHV std cell arch. CFET, BEOL w/airgaps 2D atomic channels
5T     5T <5T4T<4T
Buried power rail (BPR)    Nanosheets Forksheets Metal etch w/ airgaps Metal etch w/ airgaps
PP: Poly Pitch (nm)
MP: dense metal pitch (nm)
VHV: Vertical-Horizontal-VerticalCFET: Complementary FET
Source: IMEC, Sri Samavedam, “Future logic scaling: Towards atomic channels and deconstructed chips”, IEDM, December 2020.     Public
4

Innovation is not limited to device level    
TSMC’s system roadmap to >300 B transistors     Slide 5
29 Sept. 2021
WoW: Wafer on Wafer    CoWoS: Chip on Wafer on Substrate HBM: 3D High Speed MemoryRDL: Re Distribution Layer
SOC: System on Chip    CoW: Chip on Wafer FPGA: Field Programmable Grid ArrayInFo: Integrated Fan-Out SoIC: System on Integrated Chips
> 300 BTSMC—SoIC™ï¸
transistors
InFo    150B
transistors
CoWos    
>50 B
15Btransistors
transistors
7B    
transistors    
200 MOS transistors    
A few transistors    
3D FinFET New channel materials
HKMG     2P2EEUV
Immersion     ELKMetal oxide ESL
SiGe    Low-R Barrier Self-aligned line w/ flexible space
Cu/LowK    Co Capliner Low damage/hardening low-k & novel Cu fill
Source: Mark Liu, TSMC, “Unleash the future of innovation” ISSCC, Feb 15, 2021     Public
5

Innovation is not limited to device level    
TSMC’s system roadmap to >300 B transistors     Slide 6
29 Sept. 2021
WoW: Wafer on Wafer    CoWoS: Chip on Wafer on Substrate HBM: 3D High Speed MemoryRDL: Re Distribution Layer
SOC: System on Chip    CoW: Chip on Wafer FPGA: Field Programmable Grid ArrayInFo: Integrated Fan-Out SoIC: System on Integrated Chips
Device scaling (Including foundry supply chain)     TSMC—SoIC™ï¸
Circuit scaling (Including foundry customers)    
Dimensional scaling (Including litho supply chain)    InFo
Architectural scaling by foundry customers    
CoWos    
Chip level towards
system level
3D FinFET New channel materials
HKMG     2P2EEUV
Immersion     ELKMetal oxide ESL
SiGe     Low-R BarrierSelf-aligned line w/ flexible space
Cu/LowK     Co Capliner Low damage/hardening low-k & novel Cu fill
Source: Mark Liu, TSMC, “Unleash the future of innovation” ISSCC, Feb 15, 2021     Public
6

Moore’s Law evolution: the next decade    
Traditional scaling metrics like clock frequency have been saturated since 2005    Slide 7
29 Sept. 2021
Public dataCustomerSpeculation
1020     projection
Dennard Post Dennard
1018     scaling scaling
1016    
1014    
1012    
1010    
108    
106    
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 19902000201020202030
Source: ¹Karl Rupp as published by: Shekar Bokar, QUALCOMM, “Future of computing in the so-called post Moore’s Law era”, International conference    
for high performance computing, networking storage and analysis, November 18, 2020.     Public
7

Moore’s Law evolution: the next decade    
Scaling metric of transistor and litho density continues in this decade    Slide 8
29 Sept. 2021
Public dataCustomerSpeculation
1020     projection
DennardPost Dennard
1018     scalingscaling
1016    
1014    
1012    
1010     Transistor density2
[#/mm2]
108     Device and layout
optimizationLitho density2
106     (Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 19902000201020202030
Sources: ¹Karl Rupp 2ASML data and projection using Rupp     Public
8

Moore’s Law evolution: the next decade    
A system metric measuring energy and time efficiency combined    Slide 9
29 Sept. 2021
Energy-Efficient Performance for systems and devices defined as
[1/J.s]
If applied per single device:
EEP = fc /e
fc = clock frequency [s-1]
e = the transistor switch energy [J]
Using the Dennard¹ scaling model, when the dimension scales with k-1, frequency with k,
area with k-² and power density constant, it follows:    
EEP on-device level scales with k4
If density (~k2) scales 2x every 2 year, then EEP (~k4) scales 4x every 2 year
1Source: Robert H. Dennard et al. “Design of ion implanted MOSFET’s with very small physical dimensions”, IEEE Journal of solid-state circuits, vol SC 9, October 1973, pp. 256-268.    Public
9

Moore’s law evolution: the next decade    
Device Energy Efficient    Performance growth been saturated since 2005 Slide 10
29 Sept. 2021
Public dataCustomerSpeculation
1020     projection
DennardPost DennardSystem Energy
1018     scalingscaling Efficient Performance3
[1/J.s]
1016     From transistor to
system scaling
1014     Transistor Energy
Efficient Performance2
1012     [[1/J.s]
1010     Transistor density2
[#/mm2]
108     Device and layout
optimizationLitho density2
106     (Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 199020002010202020302040
Sources: ¹Karl Rupp, 2 ASML data and projection using Rupp     Public
10

Moore’s Law evolution: the next decade    
System Energy Efficient Performance growth 3x/2yrs continues    to 2040Slide 11
29 Sept. 2021
Source: TSMC, Mark Liu, “Unleash the future of innovation” ISSCC, Feb 15, 2021.     Public
11

Moore’s law evolution: the next decade    
From cost per transistor through density, to cost of time and energy through systems    Slide 12
29 Sept. 2021
1020     Energy
1018     Performance3
1016    
1014     tor Energy
Performance2
1012    
1010     tor density2
108     Device and layout
optimizationLitho density2
106     (Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 199020002010202020302040
Sources: ¹Karl Rupp, 2ASML data and projection using Rupp, 3Mark Liu, TSMC, normalized to transistor EEP in 2005.     Public
12

Moore’s law evolution: the next decade    
System scaling to satisfy the need for performance and energy consumption    Slide 13
29 Sept. 2021
1020    
System improvements    System System Energy
Efficient Performance3
1018    dominated by Transistor scaling scaling [1/J.s]
1016     From transistor to
system scaling
1014     Transistor Energy
Efficient Performance2
1012     [[1/J.s]
1010     Transistor density2
[#/mm2]
108     Device and layout
optimizationLitho density2
106     (Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 199020002010202020302040
Sources: ¹Karl Rupp, 2ASML data and projection using Rupp, 3Mark Liu, TSMC, normalized to transistor EEP in 2005.     Public
13

AMD 3D chiplet gives an 3.1-3.8 EEP improvement    
By integrating memory with the processor in one package    Slide 14
29 Sept. 2021
3x power reduction,    
4-25% speed improvement    
Structural silicon    
64MB L3 cache die    
Direct copper-to-copper bond    
Through Silicon Vias (TSVs) for    
silicon-to-silicon communication    
Up to 8-core “Zen 3” CCD    
“Accelerating the ecosystem”, Compute    
14

Moore’s law evolution: the next decade    
System scaling to satisfy the need for performance and energy consumption    Slide 15
29 Sept. 2021
Public dataCustomerSpeculation
1020     projection
System improvements    System System Energy
EfficientPerformance3
1018    dominated by Transistor scaling scaling [1/J.s]
1016     From transistor to
system scaling
1014     Transistor Energy
EfficientPerformance2
1012     [[1/J.s]
1010     Transistor density2
[#/mm2]
108     Device and layout
optimizationLitho density2
106     (Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 199020002010202020302040
Sources: ¹Karl Rupp, 2ASML data and projection using Rupp, 3Mark Liu, TSMC, normalized to transistor EEP in 2005.     Public
15

Litho density scaling continues    in this decade
Overlay and Optical Proximity Correction    errors shrink aggressively Slide 16
29 Sept. 2021
2x every 6 years    
Source: Average customer roadmap extended by ASML extrapolation May 2021, averaged with 2020 IRDS Roadmap Mustafa Badaroglu,    
“IRDS IFT – More Moore Spring meeting, IEEE, April 21, 2020     Public
16

Memory roadmap    for the nextdecade
DRAM scaling below 10 nm and NAND    stacking continues > 600 layers Slide 17
29 Sept. 2021
DRAM    
After 10 years     NowChallenge<10 nm
1y    1z 1a1b1c1d0a
NAND    
After 10 years     NowChallenge>600layers
96    128 1762xx3xx4xx5xx6xx
Source: Sk hynix, S.H.Lee, “Memory’s journey towards the future ITC world, IEEE IRPS 21 March 21, 2021     Public
17

Projection of    lithography layers by technology
Slide 18
29 Sept. 2021
KrF
Logic     Layer stack
5 nm    3 nm 2 nm~1.5 nm1 nm
KrF
DRAM     EUV – High-NA
Layer stack
1A    1B 1C0A0BEUV
ArFi
ArF
KrF
KrF I-Line
3D-NAND     Layer stack
176L    2xxL 3xxL4xxL5xxL
2021     ~2030
Source: ASML Corporate Strategy and Marketing estimates     Public
18

Projection of lithography    layers by technology
Lithography layer count grows, driven by DUV and EUV     Slide 19
29 Sept. 2021
KrF
Logic     Layer stack
5 nm    3 nm 2 nm~1.5 nm1 nm
KrF
DRAM     EUV – High-NA
Layer stack
1A    1B 1C0A0BEUV
DUV
KrF
3D-NAND     Layer stack
176L    2xxL 3xxL4xxL5xxL
2021     ~2030
Source: ASML Corporate Strategy and Marketing estimates     Public
19

Semiconductor and shrink roadmap: the next decades
Slide 20
29 Sept. 2021
In the next decade, system scaling continues to fuel the need
10âµ    
1962    of advanced semiconductor solutions where litho shrink
component 10â´     remains key to improving circuit density and cost.
per    1965
cost 10³    
10²     1970
manufacturing     Implications for ASML
Relative 10     The shrink roadmap requires innovation to improve litho
1     performance at lower cost and higher productivity.
1    10 10² 10³10â´ 10âµ
Number of components per integrated circuit
We continue to safeguard our approach by developing trusting
relationships with customers, with stronger holistic products.
20

Moore’s Law evolution and customer roadmap
• ASML’s strategic priorities
21

ASML’s strategic priorities    
Slide 22
29 Sept. 2021
Strengthen    â–ª Enhance execution capabilities to deliver performance, cost
customer trust     and robustness to customers needs
Holistic litho and    â–ª Build a leading position in edge placement error
applications    
DUV    â–ª Drive DUV performance and market share
competitiveness    
EUV    
industrialization    â–ª EUV high-volume production performance, ramp and support
High-NA    â–ª Enable litho simplification for future nodes
Public
22

Our holistic portfolio    is more important than ever
Lithography scanner with Slide 23
29 Sept. 2021
advanced control capability
Etch and
deposition tools
Process window     Process window
Prediction and     Control
Enhancement    
Optical proximity correction     ieldStar E-beam
Computational lithography     Optical metrology
computational metrology     E-beam metrology
E-beam inspection
Process window
Detection
Public
23

Our    holistic portfolio ismore importantthanever
Slide 24
29 Sept. 2021
EUV     DUV
High-NA    
Applications
Public
24

Applications: strategic directions    
Deliver leading solutions for optical and e-beam metrology and inspection    Slide 25
APPS     29 Sept. 2021
Customer Value     ASML Apps product roadmap
Capturing more wafer signatures to    • Productivity
improve robust on-wafer process control    • Robust alignment schemes
Nanometers    
Tighter process capabilities    • Single Beam resolution and applications
3→6 sigma control    • Edge Placement Error control
• Free-Form OPC and Machine Learning
Good wafers    Capturing small defects for •Multibeam resolution
per day per    yield of advanced nodes •Computationally guided inspection
unit cost    
More measurements at fixed    • Productivity/multibeam
metrology & inspection budget    • E-beam platform consolidation
• OPC accuracy, speed and user-friendliness
Faster time-to-solution    
Time to yield     •Single process control platform and analytics
Public
25

E-beam inspection has inherent resolution advantage    
Increasing throughput through increasing parallelism with multibeam     Slide 26
APPS     29 Sept. 2021
1000000 Min defect size for
2 nm node and below
100000 Optical
Bright Field
10000 Inspection
1000 Gen 3 Multibeam (~2028)
100 Increased
[mm²/hr]     throughput
enables
10 additional HVMGen 2 Multibeam (~2024)
ghput     applications
Throu    1
0.1 Gen 1 Multibeam (2021)
0.01 Scanning
electron
microscope
0.001 imageSingle e-beam (R&D)
0.0001
60 40201086421
Defect size [nm]Public
26

Metrology, Inspection & Patterning Control Roadmap    
Slide 27
APPS     29 Sept. 2021
2020    2021 202220232024³ 2025
Scanner Interfaces    
and Control Software     Increasing Scanner Actuation (DUV and EUV), EPE Control
Overlay Metrology     Fast Stages, Multiple Wavelengths, Computational Metrology,
YieldStar     In-Device Metrology
E-beam    eP5 0.1nm precision, 12umSinglefield of vi w, Beam9K V HLE (option)High Resolution, LargeeP6FieldHigh r Precision,of View,High r Resolution eP7 Next Generation
Metrology     Massive Metrology, EPE metrologyeP7XLE
eP5XS 18.5KeV landing energy    eP5XLE 30KeV landing energy
50KeV landing energy
E-Beam Defect    
Inspection     Multi-beam, Fast and Accurate Stages, High Landing Energy, Guided Inspection
Computational     Improved Model Accuracy, Inverse OPC,
Lithography     Machine and Deep Learning, Etch Models
Public
27

NXT:2050i in volume manufacturing at customers    
DUV    20% overlay improvement, faster reliability and productivity ramp-up Slide 28
29 Sept. 2021
NXT:2050i
Matched machineDedicated chuck
overlay ~1.2 nmoverlay ~0.8 nm
6000    5,000 wafers per day in 18 days 200180 hours reliability in 13 weeks
180
5000    NXT:2050i 160NXT:2050i
Faster ramp 140Higher availability
4000    
120
per day     (hours)
3000     100
Wafers     MTBI 80
2000    
60
40
1000    
20
0     0
1 2 3    4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 NXT:2000i1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 1718 19
Days after completing installation Weeks after completing installation
NXT:2050iPublic
28

DUV: Strategic directions    
DUV    Deliver leading solutions for advanced capabilities and higher productivity Slide 29
29 Sept. 2021
Customer value ASML DUV product roadmap
Overlay    Improve overlay (stability) especially •NXT:2100i with optics and alignment improvements
for matching to EUV
Productivity &    More good wafers per day at •Immersion productivity increase through
Availability    lower cost per wafer higher scan speed
•XT to NXT transition for dry lithography
Installed base    Cost-competitive service offerings for •Productivity Enhancement Packages for installed base
entire product lifecycle •Value added service solutions increasing availability at
node performance
New markets    Productivity and overlay performance for •Mature XT platform with application specific options
specific applications •Extend i-line product portfolio for Mature markets (>40nm)
•Fab replacement solutions
Circular    Sustainable product & service offerings •System Node Extension Package roadmap
economy     •Optimize re-use to secure cost competitive supply
Public
29

DUV    product portfolio to support all market segments
DUV     Slide 30
29 Sept. 2021
ength    NA, Half pitch 202020212022202320242025
Continue innovationNXT:2000i on advanced NXT:2050i NXT platform for improved NXT:2100i imaging, overlay and productivity NEXT
critical
ArFi    1.35 NA,38 nm2.0 nm | 275wph1.5 nm | 295wph1.3 nm | 295wph
Leveragemid—c itical of NXT:1980Di advanced NXT platform forNXT:1980Ei improved productivity NXT:1980Fi
2.5 nm | 275wph2.5 nm | 295wph2.5 nm | 330wph
XTXT:1460K
ArF    0.93 NA,57Migratenm to advanced 5 nm | 205wph NXTor platform 7.5 nm| 228wph for improved imaging, overlay and productivity
NXT:1470NEXT
NXT4 nm | 300wph
0.93    NA, 80ProductivitynmXT:1060K increases on XT platformXT:1060K + PEP
5 nm | 205wph5 nm | 220wph
KrF     XTXT:860MXT:860N
Productivity 7increasesnm** | 240 on- 250wphXT platform7.5 nm | 260wph
0.80    NA,110 nm
Migrate to advanced NXT platform for performanceNXT:870and productivityNEXT
NXT7.5 nm | 330wph
i-line    0.65 NA,220ProductivitynmXT:400L increases on XT platform and migrate to next systemXT:400M for high volume applications NEXT
20 nm** | 230wph20 nm** | 250wph
27%34%30%
66%70%
Public
30

EUV 0.33 NA adoption enabled by platform maturity in    
EUV    high-volume manufacturing Slide 31
29 Sept. 2021
100%
3000    System output
Max wafers per day (single system, weekly average) 95%
2500     90%
Installed base system availability
day    4 weeks moving average (end of period) 85%
2000    
per     80%
1500     75% Availability
Wafers     70%
1000     65%
60%
500    
55%
0     50%
2017    2018 201920202021
ASML commitment is expected to bring EUV availability >95%    
and increase wafer per day output >50% by 2025
Source : ASML installed base data     Public
31

EUV: strategic directions    
EUV Enabling cost-efficient scaling for advanced nodes    Slide 32
29 Sept. 2021
Customer value using EUV    ASML EUV product improvements
Better device performance: simpler    • Technology roadmap: per node (resolution), improve
design and superior electrical    imaging, overlay and defectivity (reticle and wafer
Nanometers    performance level)
Less tools needed to meet fab capacity    
due to higher throughput    • Productivity roadmap over time: increase Productivity
Productivity     to >200wph, Availability to >97%
Patterning cost saving for critical layers vs    Improvement sub system focus:
alternatives (3x ArFi immersion and    
above)    
Good wafers     • Source (in-line refill, higher power, high reflective mirror)
per day per cost    Higher yield due to less multiple • Mirrors (mirror heating measure, cooled mirrors)
patterning layers (up to 9%)    
• Stages and reticle (Reticle heating, high-accurate fast
stages, pellicle durability)
Reduced process complexity leading to    • Alignment (# marks, mark size, wafer clamp robustness)
Cycle time and    shorter learning cycles and faster time-to-
time to market    yield
Public
32

High-NA to prevent cycle time and process complexity increase
EUV    like low NA did for immersion Slide 33
29 Sept. 2021
5     Insertionpreferred
EUVEUV
NANA
3     --
u. )     0.330.55
(a. dependent)     DUVEUV- 0.33NAEUV- 0.55NA
complexity cycletime (product    3
0.33-NA insertion supports singleHigh-NA insertion opportunities to
process steps,     patterning to reduce cycle timecontinue Moore’s Law without any
mask     penalty of cycle time increase
2    
AlternativeAlternative
Proposed baselineProposed baseline
1    
10     1001,000
16nm    10nm 7nm5nm3nm2nm
Transistor density [MTr/mm²] Nodes (equivelant node names) [nm]
Note: Assuming 1.2 days per mask layer     Public
33

High-NA EUV: strategic directions    
EUV Enabling cost-efficient scaling for next generation advanced nodes    Slide 34
29 Sept. 2021
Customer value High-NA EUV    ASML High-NA EUV product improvements
0.55 NA enables 1.7x smaller features    
and 2.9x increased density    • Technology roadmap: per node (resolution), improve
Nanometers     imaging, overlay and defectivity (reticle and wafer
level)
Higher imaging contrast enables 40%    
improvement in local CDU    • Productivity roadmap over time: increase Productivity
Performance    1.4x reduced pattern variability at 1.4x
lower dose    
15% Patterning cost saving for critical    Focus for a successful insertion at
layers vs alternatives (2x EUV)    our customers
Good wafers     •Commonality with existing EUV platform to reduce
per day per cost    Higher yield due to less multiple technological risk, cost of development and switch cost
patterning layers: 35% less mask count     at customer
below 2 nm process node    
• Focus on system maturity and serviceability to support
Reduced process complexity leading to     our customer high volume performance expectation
Cycle time and    15% shorter learning cycles and faster •Early engagement with our customers to address
time to market    time-to-yield ecosystems readiness
Public
34

High-NA EUV is in the realization    phase
EUV On multiple ASML and supplier locations     Slide 35
29 Sept. 2021
Oberkochen, Germany optics system manufacturing facilities    
Veldhoven,
the Netherlands,
system bottom test
EUV 0.55 NA optics    
Toulon, France, Frame milling     Wilton, USA,system top test
Public
35

EUV 0.55 NA is expected to be added to EUV portfolio    
EUV    for high volume in 2025—2026 while continue improving the 0.33 NA platformSlide 36
29 Sept. 2021
2020    2021 202220232024³2025
0.33NA continuous imaging,NXE:3600Doverlay and productivity improvementsNXE:3800E in line     NXE:4000F
with customers advanced1.1 nmnode| 160HVMwph requirements.    <1.1 nm | >195 wph / 220wph <0.8nm|>220wph
EUV     ASMLR&DHVM
0.55NA    enabling affordable scaling beyond current decade
EXE:5000EXE:5000 EXE:5200
at ASML fab<1.1 nm | 150 wph <0.8 nm | 220 wph
EXE platform, EUV 0.55 NA     NXE platform, EUV 0.33 NA
Public
36

ST    Commonality across EUV, DUV & High-NA platforms
Slide 37
TRU    Allows faster and more cost-effective innovation, production and maintenance 29 Sept. 2021
DUV     EUV
Alignment Sensor
Common Technology    Level sensor
used in both    Metrology
DUV & EUV platform    Wafer handling
NXT (193 nm dry)
Common Technology    
used in    
DUV products: NXT    
NXT:870    NXT:1470 NXT:2050i
EUV     EUV High-NA
Alignment Sensor Source
Level sensor Metrology
Common Technology    Wafer stager
used in both    Reticle stager
EUV platforms    Wafer handling
37

ST    Maximizing customers’ good wafers per day
Slide 38
TRU    Next to minimizing system down time 29 Sept. 2021
100% 100%100%
System downtime     System downtime serving
according to     customer needs
standardized    
definition    >97% Process-specific inefficiencies
e.g., system down to meet
customer specs, layer
qualification after system down,
defectivity monitoring and more > 90-95%
> 85-90%
System uptime     System uptime producing
capable of producing     customer wafers
wafers    
Historical service model:    New service model:
Maximize scanner availability    Maximize good wafers per day
Public
38

ST    EUV is the most energy efficient solution
Slide 39
TRU    We expect net energy savings of more than 45% over alternative processes 29 Sept. 2021
EUV 0.33EUV 0.55
Electrical power reduction     Electrical power reduction
Immersion to EUV 0.33 productivity [wph]     EUV 0.33 to EUV 0.55 at 220 wph
Side wall Assisted     DryEtch
Quadrupole Patterning     ArFi
EUVLito-Etch-Litho-Etch 0.33 NA - 46%
100 wph     - 45%Metallization
MetrologyLitho-Etch 0.55 NA
145 wph     Deposition
(today)     05101520
WetEtch
220 wph    
(2025)    
0    5 101520
Source: Sri Samavedam a.o., IMEC, “Future of logic scaling: Towards atomic channels and deconstructed chips”, IEDM, Dec 2020, extended by ASML.     Public
39

Technology strategy    
Holistic Lithography roadmap is driven by our unique
Key messages     patterning control solutions that deliver customer value viaSlide 40
29 Sept. 2021
improved on product performance.
• Moore’s Law is alive and well! Industry innovation    • ASML’s comprehensive product portfolio is aligned to our
continues, fueled by system scaling, delivering highly valued     customers’ roadmaps, delivering cost effective solutions in support
semiconductor products.     of all applications from leading edge to mature nodes
• Semiconductor system scaling enables exponential    • Our next generation EUV technology, High-NA, is progressing
performance improvement and energy reduction in support of     well and will be the engine to drive the lithography roadmap into
significant growth of data exchange.     the next decade
• Customers’ roadmaps require continued shrink and    • Continued execution of our strategic priorities is expected to
reduction in edge placement error to drive affordable scaling     provide cost effective solutions for our customers, enable the
into next decade.     extension of the industry roadmap into the next decade, and
support our long-term sustainability commitment
40

Forward Looking Statements    
Slide 41
29 Sept. 2021
This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including     expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue     opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-     2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected     annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long     term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor     end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand     growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and     DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated     wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues     and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output     capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s     law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy,     dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and     growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify     these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”,     “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on     current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them.     Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and     uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing     capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our     customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets,     as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability     to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and     demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized     in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain     capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the     outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor     markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets,     changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for,     and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in     ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission.     These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of     this report or to conform such statements to actual results or revised expectations, except as required by law.     Public
41

ASML SMALL TALK 2021 42

Exhibit 99.4

EUV Products and Business Opportunity Christophe Fouquet Executive Vice President Business Line EUV

EUV products and business opportunity Key messages Slide 2 29 Sept. 2021 ASML EUV lithography extends our Logic and DRAM customers roadmap by providing lithography resolution improvement, state of the art overlay performance and year on year cost reduction Our customers are using EUV in Logic node and starting to use EUV in DRAM node in 2021. EUV layers adoption continues to grow to reduce patterning complexity and cost ASML EUV capability ramp combined with its productivity roadmap expected to support our customers surging demand in the coming years EUV product roadmap expected to extend our EUV platform and introduce EUV 0.55 NA platform in parallel to provide comprehensive and flexible solutions to our customers’ continuous demand for patterning scaling well into the next decade We expect to continue to improve EUV profitability over time through the combined execution of our value enhancing product roadmap and ambitious systems and service cost reduction roadmap Public

EUV 0.33 NA is in production for both Logic and DRAM, and its adoption is expected to continue to grow EUV 0.33 NA extension and EUV 0.55 NA introduction is expected to extend EUV values to the next decade Our increased EUV product and service value is expected to continue to drive profitability

EUV 0.33 NA is in production, for both Logic and DRAM All advanced semiconductor manufacturers expected to run EUV in Slide 4 29 Sept. 2021 production by 2024 Fastest, Largest-capacity Mobile Memory Based on today’s most advanced (1z) process node, Samsung’s new 16Gb LPDDR5 is the first memory to be mass produced using EUV technology, providing the highest speed and largest capacity available in mobile DRAM. Source: Samsung, press release, Korea August 30, 2020 Source: Apple, press release, November 10, 2020 SK Hynix starts Mass production of 1anm DRAM using EUV Equipment SK Hynix, Seoul, July 12, 2021 Micron announces EUV fabs by 2024 Source: Intel, Pat Gelsinger, “Engineering the future”, March 23, 2021 Source:The Register, Jul 2021 Public

EUV 0.33 NA adoption enabled by platform maturity in high-volume manufacturing Slide 5 29 Sept. 2021 100% 3000 System output 95% Max wafers per day (single system, weekly average) 2500 Installed base system availability 90% day 4 weeks moving average (end of period) 85% 2000 per 80% 75% 1500 Availability Wafers 70% 1000 65% 60% 500 55% 50% 0 2017 2018 2019 2020 2021 ASML commitment is expected to bring EUV availability >95% and increase wafer per day output >50% by 2025 Source : ASML installed base data Public

EUV 0.33 NA adoption expected to continue for Logic and DRAM to support most advanced device roadmap Slide 6 29 Sept. 2021 30 Actuals Today Roadma 20 Logic exposures Memory of max min Number 10 0 2018 2019 2020 2021 2022 2023 20242025 Public

EUV increased adoption expected to result into >2x increase of EUV wafer moves per year 2025 compared to 2021 Slide 7 29 Sept. 2021 800% 30 Actuals Today Roadmap (ambition) year Memory per 20 Logic exposed exposures Memory of max wafers min 10 EUV Number Logic Total 100% 0 2018 2019 2020 2021 2022 2023 2024 2025 Public    

ASML to address EUV demand by increasing shipments and system productivity Slide 8 29 Sept. 2021 Actuals Today Roadmap 400% (ambition) [#] year wph*] 300% per[ put Through 200% ents/Capacity Shipm System |100% 2018 2019 2020 2021 2022 2023 2024 2025 NXE:3400B NXE:3400C NXE:3400C NXE:3600D NXE:3600D NXE:3800E NXE:3800E NXE:4000F *wph = wafers per hour Public

ASML to address EUV demand by increasing shipments and system productivity Slide 9 29 Sept. 2021 800% Actuals Today Roadmap (ambition) 700% year [#] Fab Model: EUV estimated (3600D) wph] x Fab Capacity Exposures System Memory per 600% year (kwspm*) per fab wph] [units per[ 45 10-20 9-18 Logic put 500% exposed Memory capacity 400% 100 1-6 2-9 Through wafers 300% wafer ents/Capacity EU EUV Shipm System 200% 100%* Logic Total 2018 2019 2020 2021 2022 2023 2024 2025 NXE:3400B NXE:3400C NXE:3400C NXE:3600D NXE:3600D NXE:3800E NXE:3800E NXE:4000F * 2018 reference=100% Public    

Higher than previously projected DRAM adoption will be an additional driver for EUV demand Slide 10 29 Sept. 2021 800% Actuals Today 700% year Memory per 600% 500% exposed 400% wafers 300% EUV 200% Logic Total 100% 2018 2019 2020 2021 2022 2023 2024 2025 Public

EUV reduces lithography and process steps resulting in significant defect, cost and cycle time reduction Slide 11 29 Sept. 2021 No EUV – EUV (0.33 NA) Critical Total 120% litho masks process steps # Process stepsNo EUV No EUV 100% No EUV EUV (0.33 NA) EUV 80% (0.33 NA) EUV (0.33 NA) 60% EUV value to customers 40% No EUV Less defects 20% EUV based Cost reduction 0% Shorter cycle time Node (DRAM) Public    

Samsung reported >20% defect reduction at EUV introduction versus multi-patterning immersion (ArFi) Slide 12 29 Sept. 2021 Eliminating multi-patterning related defects Defects ratio Patterning ArFi MPT EUV SET> 20% DRAM D1xBLP [%] SEM Image ration Defects Enhancing patterning precision and cost BLP ArFi MPT EUV SET ArFi EUV Reducing number of steps and accumulated defects Source: Samsung investor Forum, November 2020 Public

EUV is in production for both Logic and DRAM, and its adoption is expected to continue to grow EUV extension and EUV 0.55 NA introduction is expected to extend EUV values to the next decade Our increased EUV product and service value is expected to continue to drive profitability

ASML is expected to continue to extend DUV and EUV platforms at the pace required by our customers Slide 14 29 Sept. 2021 mWavelength NA, Half pitch 2020 2021 2022 2023 2024 ³2025 DUV NXT:2000i NXT:2050i NXT:2100i NEXT 1.35 NA, 38 nm 2.0 nm | 275wph 1.5 nm | 295wph 1.3 nm | 295wph (ArFi) NXE:3400C NXE:3600D NXE:3800E NXE:4000F EUV 0.33 NA, 13 nm 2 3 3 <0.8 nm | >220wph 1.5 nm | 135 wph / 145wph 1.1 nm | 160wph <1.1 nm | >195wph / 220wph wafers/hours (wph) are based on 30mJ/cm² 1) 185wph@20mJ/cm² 2) 170wph@20mJ/cm² 3) Throughput upgrade Product: Matched Machine Overlay (nm)|Throughput(wph) Product status Released Development Definition Public

EUV 0.55 NA is expected to be added to EUV portfolio to support high-volume manufacturing in 2025—2026 Slide 15 29 Sept. 2021\ Wavelength NA, Half pitch 2020 2021 2022 2023 2024 ³2025 NXE:3400C NXE:3600D NXE:3800E NXE:4000F 0.33 NA, 13 nm 2 3 3 <0.8 nm | >220wph 1.5 nm | 135 wph / 145wph 1.1 nm | 160wph <1.1 nm | >195wph / 220wph Early Access Customer Customer EUV Customer timing 0.55 NA ASML R&D HVM EXE:5000 EXE:5000 EXE:5200 0.55 NA, 8 nm 1 at ASML fab <1.1 nm | 150wph <0.8 nm | 220wph EUV 0.55 NA higher resolution enables 1.7x smaller features and 2.9x increased density wafers/hours (wph) are based on 30mJ/cm² EUV 0.55 NA higher imaging contrast 1) 185wph@20mJ/cm2 2) 170wph@20mJ/cm² enables 40% improvement in local CDU 3) Throughput upgrade and improves productivity on critical layers Product: Matched Machine Overlay (nm)|Throughput(wph) Product status Released Development Definition Public

EUV 0.55 NA expected to once again reduce litho and process steps at the horizon of 2025—2026 for both Logic and DRAM Slide 16 29 Sept. 2021 Critical litho masks Total process steps EUV value to customers 120% EUV EUV Less defects No EUV (0.33 NA) No EUV (0.33 NA) 100% EUV EUV Cost reduction (0.33 NA) (0.55 NA) EUV 80% EUV (0.55 NA) (0.33 NA) Shorter cycle time 60% m40% 20% No EUV 0% EUV (0.33 NA) EUV (0.55 NA) 2021 2025-2026 2021 2025-2026 DRAM expectations DRAM expectations Public

EUV 0.55 NA is an evolutionary step on EUV technology, we have the source, we developed new optics Slide 17 29 Sept. 2021 NXT EUV 0.33 NA EUV 0.55 NA System changes platform to platform High 193 nm deep UV light 13.5 nm EUV light 13.5 nm EUV light Source Many Existing changes technology Source: different interface Low High Atmospheric condition Vacuum condition Vacuum condition Many Existing Scanner changes technology Higher acceleration/speed stages Low High Transmissive optics Reflective optics Reflective optics Many Anamorphic mirrors with Optics New optics changes more accuracy Low Public

A large part of our EUV 0.55 NA platform is expected to be common with our EUV 0.33 NA reducing introduction risk, cost and R&D Slide 18 29 Sept. 2021 RETICLE HANDLING RETICLE STAGE PROJECTION OPTICS BOX ILLUMINATION SOURCE WAFER HANDLING WAFER STAGE DRIVE LASER Specific Common Public

EUV optical projection mirrors ASML and Zeiss cooperation on mirror design and unique metrology system Slide 19 29 Sept. 2021 EUV 0.55 NA mirror metrology fully operational at Zeiss Public

EUV optical projection mirrors Mirrors of unprecedented size and accuracy Slide 20 29 Sept. 2021 EUV 0.55 NA optics: 1m diameter with accuracy of 20pm If you were to enlarge these mirrors to the size of planet Earth, the biggest aberration would be the diameter size of a human hair Public

Facilities for integration of EUV 0.55 NA in progress Slide 21 29 Sept. 2021 Cleanroom, Fab ASML Veldhoven Public

EUV 0.55 NA manufacturing is expected to improve quality and cycle time through integrations of 4 pre-qualified modules Slide 22 29 Sept. 2021 Pre-qualified module: RETICLE Pre-qualified Pre-qualified module : OPTICS module: SOURCE Pre-qualified module : WAFER Integration is now ongoing at ASML for all 4 pre-qualified modules RETICLE OPTICS WAFER SOURCE SOURCE SOURCE Top Frames, Wilton Integration, Oberkochen Metro frame, Veldhoven Optical Platform, San Diego Drive Laser, Veldhoven Vessel, San Diego Public

EUV is in production for both Logic and DRAM, and its adoption is expected to continue to grow EUV extension and EUV 0.55 NA introduction is expected to extend EUV values to the next decade Our increased EUV product and service value is expected to continue to drive profitability

Increased EUV product and service value combined with Slide 24 cost reduction expected to drive better profitability 29 Sept. 2021 400% Actuals Today Roadmap 300% day** per ghput 200% 2 nm wafer[nm] throu rlay Average stem 100% 1 nm Ove Sy 2018 2019 2020 2021 2022 2023 2024 2025 NXE:3400B NXE:3400C NXE:3400C NXE:3600D NXE:3600D NXE:3800E NXE:3800E NXE:4000F* Normalized with 2018 and based on 30 mJ Public

EUV products and business opportunity Key messages Slide 25 29 Sept. 2021 ASML EUV lithography extends our Logic and DRAM customers roadmap by providing lithography resolution improvement, state of the art overlay performance and year on year cost reduction Our customers are using EUV in Logic node and starting to use EUV in DRAM node in 2021. EUV layers adoption continues to grow to reduce patterning complexity and cost ASML EUV capability ramp combined with its productivity roadmap expected to support our customers surging demand in the coming years EUV product roadmap expected to extend our EUV platform and introduce EUV 0.55 NA platform in parallel to provide comprehensive and flexible solutions to our customers’ continuous demand for patterning scaling well into the next decade We expect to continue to improve EUV profitability over time through the combined execution of our value enhancing product roadmap and ambitious systems and service cost reduction roadmap Public

Forward Looking Statements Slide 26 29 Sept. 2021 This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy, dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”, “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets, as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets, changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for, and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of this report or to conform such statements to actual results or revised expectations, except as required by law. Public

ASML Small Talk 2021 Investor Day Virtual

Exhibit 99.5

Applications Products and Business Opportunity Jim Koonmen Executive Vice President Business Line Applications

Applications products and business opportunity Key messages Slide 2 29 Sept. 2021 The Applications business is projected to grow at ~20% CAGR with strong gross margins over the period 2020 through 2025 The Applications product portfolio supports the ASML scanner business, driven by our unique capability to help customers maximize patterning performance    Driving improvements in Edge Placement Error (EPE)    Delivering leading solutions for optical and e-beam metrology and inspection    Integrating ASML’s complete product portfolio into a Holistic Litho solution to optimize and control the litho process Primary drivers of growth are the extension of our EPE roadmap:    New metrology, inspection and control offerings extend the roadmap    Innovative products combine computational technology, YieldStar overlay metrology and e-beam metrology    Hardware and software products support the introduction of EUV into HVM    New applications of deep learning in both computational litho and defect inspection drive improved performance Public

Markets and product roadmap Holistic lithography Driving improvements in EPE E-beam inspection

Growth opportunities in Applications arise from technology shifts in key market segments Slide 4 29 Sept. 2021 Industry driver Technology shifts Resolution Throughput HighResolutio Single Beam / Optical Multibeam Parts per billion failure Inspection measurements Optical Overlay: Image-based to Accuracy diffraction-based Optical and E-beam Precision Optical Overlay: Targets Device Metrology Massive metrology E-beam: Small field Large field Market TAMs Physical models Deep learning Computational Model accuracy Rectangular Freeform mask patterns Lithography Compute cost 4.0B CPU Hybrid/GPU compute 3.3B Transition to EPE Overlay / CD EPE Scanner and EUV to HVM HVM: DUV DUV + EUV Process Control Software Advanced corrections Low Higher order scanner corrections 2017 2020 2025 Public TAM based on ASML interpretation of VLSI Research and Gartner

Metrology, Inspection & Patterning Control Roadmap Slide 5 29 Sept. 2021 2020 2021 2022 2023 2024 ³ 2025 Scanner Interfaces Increasing Scanner Actuation (DUV and EUV), EPE Control and Control Software Overlay Metrology Fast Stages, Multiple Wavelengths, Computational Metrology, YieldStar In-Device Metrology E-beam Single Beam High Resolution, Large Field of View, Metrology Massive Metrology, EPE metrology E-Beam Defect Multi-beam, Fast and Accurate Stages, High Landing Energy, Guided Inspection    Inspection Computational Improved Model Accuracy, Inverse OPC, Lithography Machine and Deep Learning, Etch Models Public

Markets and product roadmap    Holistic lithography Driving improvements in EPE E-beam inspection

Our holistic portfolio is more important than ever Lithography scanner with Slide 7 29 Sept. 2021 advanced control capability EUV: NXE and DUV: XT and Etch and EXE platforms NXT platforms deposition tools Process window Process window Prediction and Control Enhancement Overlay Optical proximity correction CD YieldStar E-beam Computational lithography Optical metrology and computational metrology E-beam metrology E-beam inspection Process window Detection Public

Our holistic portfolio is more important than ever Lithography scanner with Slide 8 29 Sept. 2021 advanced control capability EUV: NXE and DUV: XT and Etch and EXE platforms NXT platforms deposition tools Process window Process window Prediction and Control Enhancement Optical proximity correction YieldStar E-beam Computational lithography Optical metrology and computational metrology E-beam metrology E-beam inspection Process window Detection Public

Our holistic portfolio is more important than ever Lithography scanner with Slide 9 29 Sept. 2021 advanced control capability EUV: NXE and DUV: XT and Etch and EXE platforms NXT platforms deposition tools Process window Process window Prediction and Control Enhancement Optical proximity correction YieldStar E-beam Computational lithography Optical metrology and computational metrology E-beam metrology E-beam inspection Process window Detection Public

All data available at every step in the flow Use scanner metrology, YieldStar, HMI metrology and inspection to optimize Slide 10 29 Sept. 2021 sampling for scanner control, and as yield proxy for faster time-to-yield After-etch After-etch / CMP Computational After-litho After-etch Lithography Etch e-beam e-beam lithography metrology metrology metrology inspection Recipe Recipe Recipe Recipe Recipe Recipe Data Data Data Data Data Data Data Virtual Computing Platform HMI e-beam HMI e-beam Holistic Scanner YieldStar Hybrid Metro Metrology Inspection applications applications applications applications VCP applications applications Single user interface, common features, control framework—through each and every step ASML Shared functions and (domain) models Analytics foundation Data infrastructure Equipment and automation integration, security, data solutions Customer generic computing hardware Customer Public

Markets and product roadmap Holistic lithography    Driving improvements in EPE E-beam inspection

Reducing Edge Placement Error (EPE) is key to improve yield Local CD errors, due to stochastics, become increasingly important Slide 12 29 Sept. 2021 nm 250 Edge Placement Error (EPE): combined error of overlay and CD uniformity (global EPE is the best predictor of yield CDU, local CD errors and OPC error) CD: Critical Dimension, OPC: Mask Optical Proximity Correction Public

YieldStar overlay metrology – after litho and after etch Characterizing the process error and enabling accurate feature placement Slide 13 29 Sept. 2021 Optical overlay metrology – after Litho Optical overlay metrology – after Etch Litho Etch YS385 YS1385 Metrology Metrology Accurate overlay data Accurate overlay data on targets on actual device Corrections ~800 Points x 4 wafers ~10,000 Points x 2 wafers Every lot Every few days Litho overlay control: after Litho sparse + after Etch refine Public

Driving improvements in EPE Requires high fidelity, fast and accurate metrology to maximize the Slide 14 29 Sept. 2021 scanner’s correction capabilities Metrology Monitoring Control Overlay YieldStar Layer B to Layer A Final Dual Layer EPE Pattern as designed >1,000 measurements/wafer <5 mins Single layer EPE Layer A HMI ePx >10 million measurements/wafer 60 min Single layer EPE Layer B Wafer HMI ePx Computational EPE Signature Control Software >10 million measurements/wafer 60 min Public

ASML scanners to improve EPE and yield ASML scanners are uniquely able to find, measure and correct for Slide 15 29 Sept. 2021 patterning variations FlexRay illuminator Even Fingers Odd Fingers Dose Grey Filter Optical Ce manipulator Y    Z Reticle stage Metrology stage Exposure stage 100% of wafers 100% of wafers are are measured processed field-by-field Wafer stage Scanner actuators correct on a field-by-field basis Public

Tighter EPE requirements drive increased metrology ASML provides accurate, cost-effective overlay, EPE, and defect metrology Slide 16 29 Sept. 2021 Measurements per lot Billions Overlay EPE Defects EPE Requirement 14 12 Millions [nm] 10 8 requirement 6 Thousands EPE 4 2015 2018 2021 2024 2027 2030 2 0 Overlay 2015 2018 2021 2024 2027 2030 EPE Defect Inspection Public

Need for part per billion control stratedy Defect-aware monitoring and control in the age of EUV stochastics Today, server chips can be ~800mm2 in size    

Need for part per billion control stratedy Defect-aware monitoring and control in the age of EUV stochastics    1 mm 1 mm There can be >100M contact holes per mm2 and increasing by 1.5x per node Today, server chips can be ~800mm2 in size

Need for part per billion control strategy Defect-aware monitoring and control in the age of EUV stochastics Slide 19 29 Sept. 2021 SEM image: example missing contact hole so ~80B of these need to function There can be >100M contact holes per mm2 and increasing by 1.5x per node Today, server chips can be ~800mm2 in size

Markets and product roadmap Holistic lithography Driving EPE improvements    E-beam inspection

High resolution E-beam versus Optical bright field inspection High resolution e-beam provides superior resolution to optical inspection, Slide 21 29 Sept. 2021 enabling detection of tiny pattern fidelity defects Customer design scaling Optical bright field E-beam capable of capturing part per billion down to 10nm feature size inspection lacks sensitivity pattern fidelity defects with nanometer resolution Metal layer design Optical bright field image High resolution e-beam image Design-based inspection Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography, 97780O (21 April 2016) Public

E-beam inspection has inherent resolution advantage Increasing throughput through increasing parallelism with multibeam Slide 22 29 Sept. 2021 1000000 Min defect size for 2 nm node and below 100000 Optical Bright Field Inspection 10000 1000 Gen 3 Multibeam (~2028) Increased 100 [mm²/hr] throughput enables 10 additional HVM Gen 2 Multibeam (~2024) ghput applications Throu 1 0.1 Gen 1 Multibeam (2021) Scanning 0.01 electron microscope 0.001 image Single e-beam (R&D) 0.0001 60 40 20 10 8 6 4 2 1 Defect size [nm] Public

E-beam inspection: Voltage Contrast (VC) and physical defect Unique capability of electron beam inspection to find yield limiting defects Slide 23 29 Sept. 2021 VC inspection: detection of interlayer Physical inspection: detection of intralayer defects causing electric opens and shorts defects such as design and process weak spots eScan eScan ePx    Heavily used in DRAM and 3D NAND    Used in all market segments    HMI is the technology leader in e-beam inspection    HMI leadership enabled by high current, charging control, and fast data rates Public

Multibeam addresses both VC and physical defect inspection Delivering cost-effective throughput gains at high resolution Slide 24 29 Sept. 2021 VC inspection: detection of interlayer Physical inspection: detection of intralayer defects causing electric opens and shorts defects such as design and process weak spots eScan eScan ePx P(-1,1) P(0,1) P(1,1) P(-1,0) P(0,0) P(1,0) eScan P(-1,-1) P(0,-1) P(1,-1) eScan multibeam multibeam Public

Multibeam leverages ASML core technologies Increasing e-beam inspection throughput for high-volume manufacturing Slide 25 29 Sept. 2021 3 Brion’s computational technology: Single beam system    Deep-learning-enabled image quality enhancement    Design-based defect inspection Throughput 2 ASML’s stage technology:    High speed motion    High position accuracy 1 HMI’s Advanced Electron Optics & MEMS High quality SEM images with 9 beams scanning simultaneously Public

Multibeam: current status Implementing learnings from eScan1000 (3x3) and driving eScan1100 Slide 26 29 Sept. 2021 (5x5) qualification for first shipment expected in Q4 2021 Key messages    Multibeam technology is challenging    We experienced some program delays: ended original development partnership, COVID    We added additional expertise to the team and developed new multibeam IP    We remain confident about multibeam and are committed to realizing its market potential Status today    3 eScan1000 prototypes (3x3 beams) running and under assessment at customers Imaging results from the    System qualification of eScan1100 (5x5 beams) eScan1100 5x5 multibeam system moving full speed; first shipment expected Q4 2021 Public

Applications products and business opportunity Key messages Slide 27 29 Sept. 2021 The Applications business is projected to grow at ~20% CAGR with strong gross margins over the period 2020 through 2025 The Applications product portfolio supports the ASML scanner business, driven by our unique capability to help customers maximize patterning performance    Driving improvements in Edge Placement Error (EPE)    Delivering leading solutions for optical and e-beam metrology and inspection    Integrating ASML’s complete product portfolio into a Holistic Litho solution to optimize and control the litho process Primary drivers of growth are the extension of our EPE roadmap:    New metrology, inspection and control offerings extend the roadmap    Innovative products combine computational technology, YieldStar overlay metrology and e-beam metrology    Hardware and software products support the introduction of EUV into HVM    New applications of deep learning in both computational litho and defect inspection drive improved performance Public

Forward Looking Statements Slide 28 29 Sept. 2021 This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy, dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”, “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets, as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets, changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for, and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of this report or to conform such statements to actual results or revised expectations, except as required by law. Public

Asml Small Talk 2021 Investor Day Vitrual

Exhibit 99.6

DUV Products and Business Opportunity Ron Kool Executive Vice President Business Line DUV ASML ASML Small Talk 2021 Investor Day Virtual

DUV products and business opportunity     Key messages Slide 2 29 Sept. 2021 DUV demand is at a record high and expected to remain strong for the foreseeable future driven by both the Advanced and the Mature market segments Innovation in technology for the Advanced Logic and Memory market will continue; we extended the roadmap on all wavelengths, with performance and productivity improvements on the NXT platform to support the industry’s cost and energy efficient scaling The Mature market including More than Moore applications presents a growth opportunity by building on the XT portfolio in combination with solutions addressing the specific requirements of market segments like power devices, sensors With the aim to optimize the installed base for our customers, there is an increased focus on value added services in combination with productivity and performance upgrades Public

Markets Advanced Logic and Memory Mature Logic and Analog nodes, and More than Moore markets Installed base Public

DUV business outlook improved significantly Driven by strong markets, increased process complexity and installed base growth Slide 4 29 Sept. 2021 2018 DUV installed base 20% DUV installed base 50% 2025 2018 50% 80% systems DUV systems In 2018 our forecast assumed a reduction in immersion demand due to EUV adoption, market growth in line with historical trends Public

DUV business outlook improved significantly Driven by strong markets, increased process complexity and installed base growth Slide 5 29 Sept. 2021 2021 DUV installed base DUV installed base 30% 25% 2025 2021 70% 75% DUV systems DUV systems Drivers include technology innovation, increase in process complexity resulting in more demand at all wavelengths, and growth in the installed base business opportunity Public

DUV addresses numerous market segments SPECIALTY MEMORY Slide 6 MATURE LOGIC 29 Sept. 2021 300 mm 300 mm 200 mm Sub—segmentation LOGIC 300 mm ANALOG Front-End Applications “More Moore” Special Applications Mature 300 mm “More than Moore” segments 200 mm Advanced POWER 300 mm (³ 40nm) MPU segments 150 mm (£28 nm) NON—OPTICAL SENSORS EUV 300 mm OPTICAL ArFi SENSORS DRAM ArF 300 mm KrF 300 mm ADVANCED I-Line PACK G NAND Source: ASML Public    

Projection of lithography layers by technology Lithography layer count grows, driven by DUV and EUV Slide 7 IR Sep 2021 KrF Logic Layer stack 5 nm 3 nm 2 nm ~1.5 nm 1 nm KrF DRAM EUV – High-NA Layer stack 1A 1B 1C 0A 0B EUV DUV KrF 3D-NAND Layer stack 176L 2xxL 3xxL 4xxL 5xxL 2021 ~2030 Source: ASML Public

Our end markets are increasingly interdependent Requiring an integral portfolio of solutions Slide 8 29 Sept. 2021 EUV 150 mm ArFi ANALOG 200 mm ArF LNA POWER diversity Mid/High OPTICAL 130 nm SENSORS 180 nm KrF LOGIC 150 mm Aperture tuner NON—OPTICAL I-Line SENSORS 45 nm 5 nm LOGIC 180 nm Public

DUV product portfolio to support all market segments Slide 9 29 Sept. 2021 Wavelength NA, Half pitch 2020 2021 2022 2023 2024 2025 NXT:2000i NXT:2050i NXT:2100i NEXT critical 2.0 nm | 275wph 1.5 nm | 295wph 1.3 nm | 295wph ArFi 1.35 NA, 38 nm NXT:1980Di NXT:1980Ei NXT:1980Fi mid—critical 2.5 nm | 275wph 2.5 nm | 295wph 2.5 nm | 330wph XT:1460K    XT 5 nm | 205wph or 7.5 nm| 228wph ArF 0.93 NA, 57 nm NXT:1470 NEXT NXT 4 nm | 300wph 0.93 NA, 80 nm XT:1060K XT:1060K + PEP 5 nm | 205wph 5 nm | 220wph XT:860M XT:860N KrF XT 7 nm** | 240—250wph 7.5 nm | 260wph 0.80 NA,110 nm NXT:870 NEXT NXT 7.5 nm | 330wph i-line 0.65 NA, 220 nm XT:400L XT:400M NEXT 20 nm** | 230wph 20 nm** | 250wph 27% 30% 34% 5% Product: Matched Machine Overlay (nm)|Throughput(wph) 95% 66% 70% Product status Released Development Definition **Wafer inner field Public

NXT transition improves KrF and ArF productivity significantly Slide 10 29 Sept. 2021 27% hour 330 per 260 Wafers KrF XT:860N NXT:870 2021 2022 hour 46% per    300 Wafers 205 ArF NXT:1470 first litho system to show >300wph XT:1460 NXT:1470 2019 2021

We will support our customers’ wafer demand By increasing factory output and scanner productivity Slide 11 29 Sept. 2021 (wph) lity    ~1.7X growth pabi ut ca outp fer ing wa productivity ctur manufa ML system AS x capability system Yearly    2019 2020 ArFi

Markets    Advanced Logic and Memory Mature Logic and Analog nodes, and More than Moore markets Installed base Public

NXT:2050i in volume manufacturing at customers 20% overlay improvement, faster reliability and productivity ramp-up Slide 13 29 Sept. 2021 NXT:2050i Matched machine Dedicated chuck overlay ~1.2 nm overlay ~0.8 nm 6000 5,000 wafers per day in 18 days 200 180 hours reliability in 13 weeks 180 5000 NXT:2050i NXT:2050i 160 Faster ramp 140 Higher availability day 4000 per 120 (hours) 3000 100 Wafers MTBI 80 2000 60 40 1000 20 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 NXT:2000i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Days after completing installation Weeks after completing installation Public NXT:2050i

NXT:2100i makes a 20% step in on product overlay vs the NXT:2050i for a typical DRAM application Slide 14 29 Sept. 2021 Reticle handler Faster conditioning and lower reticle-to-reticle temperature variation Projection optics Improved lens and cross matching Wafer table control Improved overlay & lifetime improvements 2D Reticle stage grid calibration Alignment 12 colors Reducing impact of reticle load errors 65 marks, small marks, combined on overlay layout Optical sensors Improved scanner improved camera & thermal metrology software conditioning Improved setup repro for overlay NXT:2100i Throughput ³295wph Productivity MMO £1.3nm Overlay On Product Overlay £1.4nm (DRAM) Public

NXT platform reduces capital investment, fab space NXT brings 17% footprint reduction with 100k wafer starts per month Slide 15 29 Sept. 2021 Use case: 100 kwspm 5 ArF (dry) 20 KrF layers 172m² 5 x XT:1460K (205wph) 140m² 4 x NXT:1470 (300wph) ArF(dry) ArF(dry) 482m² 14 x XT:860N (260wph) 421m² 12 x NXT:870 (330wph) KrF KrF Total Total 654m² 561m² Public

Markets Advanced logic and memory    Mature logic and analog nodes, and More than Moore markets Installed base Public    

We support the growth in mature Logic and Analog nodes delivering ~30% improved productivity for the same process capability Slide 17 29 Sept. 2021 350 NXT:1980Fi 300 XT:860N XT:400M 250 XT:1460K NXT:1960Bi hour 200 XT:860H XT:400H per XT:1450H Wafers 150 100 50 NXT XT 0 2013 2023 2013 2023 2013 2023 2013 2023 ArFi ArF KrF I-Line Public

Mature Markets: differentiated application space Strong growth expected short- and long-term driven by existing and new Slide 18 29 Sept. 2021 applications Substrate Substrate ANALOG MATURE OPTICAL NON—OPTICAL POWER Size [mm] Thickness [µm] LOGIC SENSORS SENSORS Thick 300 mm Standard (775) Si Si Si Si Thin Glass Thick AlTiC GaN on Si 200 mm Standard (725) Si Si SiGe SOI Si Si Thin Glass Ceramic SiC Thick 150 mm Standard (675) Si SiGe SOI Si Ceramic Thin GaAS Materials: Si: Silicon, AlTiC: Aluminum-Titanium-Carbon, GaN: Gallium Nitride, SiGe: Silicon Germanium, SiC: Silicon Carbid, SOI: Silicon on Insulator, GaAs: Gallium Arsenide Public

More than Moore market supported by the XT platform with application specific alignment and wafer handling options Slide 19 29 Sept. 2021 XT platform: ArF, KrF, i-line Wafer handling options Alignment options Wafer size: 150/200/300 mm Alignment through glass Wafer thickness: 0.3—1.5 mm Backside alignment Materials: Si, GaN on Si, SMASH extensions to 200 mm glass, Ceramic Power Optical Non-opt Sensors Sensors Warpage Wafer table flow and burl pitch Devices with many variations in substrate (thickness) Public

Markets Advanced Logic and Memory Mature Logic and Analog nodes, and More than Moore markets    Installed base Public

Over 1,000 systems exposed more than 1 Million wafers in 2020 16 systems exposing more than 2 million 300 mm wafers per year Slide 21 29 Sept. 2021 > 1.000.000 1.057 > 1.500.000 341 > 2.000.000 971 Wafers per year 862 Wafers per year Wafers per year 16 738 235 579 178 494 380 126 316 268 74 147 45 30 2 2 5 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20 Foundry Memory

Opportunities for the installed base productivity Wafer per day products Slide 22 Sept. 2021 Enhancement packages Wafer per day services Expand fab capacity at minimal lead time and investment Public

DUV immersion – upgrade roadmap System Node extension package Productivity package Slide 23 System modularity creates fab flexibility customers Under study 29 Sept. 2021 Matched 190wph 230wph 250wph 275wph 295wph 330wph Machine Overlay NXT:1950i 5.5 nm NXT:1960Bi 4.5 nm NXT:1965Ci 4.5 nm NXT:1970Ci 3.5 nm NXT:1980Di NXT:1980Ei NXT:1980Fi 2.5 nm NXT:2000i 2.0 nm NXT:2050i 1.5 nm NXT:2100i 1.3 nm Public

Services and upgrades extend value and life of tool Main upgrades over NXT scanner life Slide 24 29 Sept. 2021 System Service Upgrades PEP Software Example: NXT:1960Bi SNEP UVLS Upgrades revenue Service revenue System revenue 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 Product maturity UVLS: UV Level Sensor, SNEP: System Node Extension Package, PEP: Productivity Enhancement Package Public

DUV products and business opportunity Key messages Slide 25 29 Sept. 2021 DUV demand is at a record high and expected to remain strong for the foreseeable future driven by both the Advanced and the Mature market segments Innovation in technology for the Advanced Logic and Memory market will continue; we extended the roadmap on all wavelengths, with performance and productivity improvements on the NXT platform to support the industry’s cost and energy efficient scaling The Mature market including More than Moore applications presents a growth opportunity by building on the XT portfolio in combination with solutions addressing the specific requirements of market segments like power devices, sensors With the aim to optimize the installed base for our customers, there is an increased focus on value added services in combination with productivity and performance upgrades Public

Forward Looking Statements Slide 26 29 Sept. 2021 This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy, dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”, “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets, as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets, changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for, and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of this report or to conform such statements to actual results or revised expectations, except as required by law. Public

ASML Small Talk 2021 ASML Investor Day Virtual

Exhibit 99.7

ASML Installed Base Management Opportunity Wayne Allan Executive Vice President Customer Support Public Investor Day Virtual ASML Small Talk 2021

Public Installed Base Management Installed Base revenue is expected to grow ~12% CAGR (2020-2025) with a value-based service model plusproductivity and performance upgrades As Lithography is the constraint in the fab, maximizing good wafers per day is key to optimizing fab capital asset utilization and increasing customer return on investment Customer service value depends onthree fundamentals: -High availability and minimal long-term downs -Lowest possible service cost per wafer -Maximum good wafers per day Upgradesprovide an efficient means of improving system output and extending the useful life of the tool for future nodes Key messages 29 Sept. 2021 Slide 2

Installed Base business growth Maximizing service value—High availability and minimal long-term downs—Lowest possible service cost per wafer—Maximum good wafers per day Extending useful life of equipment through upgrades    

Installed Base revenue is a growing portion of ASML business Installed Base revenue expected to grow ~12% CAGR (2020 – 2025) ASML Slide 4 29 Sept. 2021 Installed Base revenue 8 € ) 6-7 (B 6 Revenue 4 2 0 2015 2016 2017 2018 2019 2020 * 2021 2025 China Europe Taiwan US Singapore South Korea Japan * 2021 financials externally published results/outlook, 2025 financials investors’ day

Services and upgrades extend value and life of tool Over DUV tool lifetime Installed Base revenue is ~130% of system sales Slide 5 29 Sept. 2021 Example: NXT:1960Bi Upgrades / Options revenue +130% Performance, productivity & lifetime extensions DUV:    Service revenue Service contract for scanner and laser, service on optics, relocations System revenue 2009 2010 2011 2012 2013 2014 2015 16 20 2017 2018 2019 2020 2021 22 20 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 Product maturity Public                

Installed Base business growth Maximizing service value—High availability and minimal long-term downs—Lowest possible service cost per wafer—Maximum good wafers per day Extending useful life of equipment through upgrades

Fabs are designed with lithography as the constraint Increasing litho availability increases customer return on investment Slide 7 29 Sept. 2021 Typical EUV wafer equipment constraints pareto Availability Buffer capacity Estimated capital expenditure 1% improvement capacity Volume Fab type (starts/month) Total (fab + NXT (DUV) in Fab capital out asset utilization equipment) NXE+NXT (EUV) afers DUV Logic 100k €16B €2B €160m W EUV Logic 100k €24B €6B €240m 1 1 2 2 1 1 1 1 2 XT                Source: Capital expenditure from ASML Market Research—NXE NXT Other Other Other Other Wet — Etch Etch Litho Litho Litho CVD CVD PVD Furnace Asher Furnace Litho is the fab constraint by design. Improvement in litho availability yields significant improvement in overall Fab capital asset utilization due to rest of Fab having buffer capacity: Litho constraint Litho constraint

Fabs are designed with lithography as the constraint Increasing litho availability increases customer return on investment Slide 8 29 Sept. 2021 Typical EUV wafer equipment constraints pareto Availability Buffer capacity Estimated capital expenditure 1% improvement capacity Volume Fab type (starts/month) Total (fab + NXT (DUV) in Fab capital out asset utilization equipment) NXE+NXT (EUV) afers DUV Logic 100k €16B €2B €160m W EUV Logic 100k €24B €6B €240m 1 1 2 2 1 1 1 1 2 XT
Source: Capital expenditure from ASML Market Research—NXE NXT Other Other Other Other Wet — Etch Etch Litho Litho Litho CVD CVD PVD Furnace Asher Furnace Litho is the fab constraint by design. 1% improvement in litho availability yields significant improvement in overall Fab capital asset utilization due to rest of Fab having buffer capacity:

Fabs are designed with lithography as the constraint Increasing litho availability increases customer return on investment Slide 9 29 Sept. 2021 Typical EUV wafer equipment constraints pareto Long-term downs (XLD) Buffer capacity Estimated capital expenditure 50% ↓ in XLD capacity Fab Volume ↓buffer capacity Type (starts/month) Total (fab + NXT (DUV) by 10%-15% out equipment) NXE+NXT (EUV) afers DUV Logic 100k €16B €2B €140-210m W EUV Logic 100k €24B €6B €180-270m 1 1 2 2 1 1 1 1 2 XT                Source: Capital expenditure from ASML Market Research—NXE NXT Other Other Other Other Wet — Etch Etch Litho Litho Litho CVD CVD PVD Furnace Asher Furnace Reducing long-term downs reduces need for excess capacity in non-litho workstations which saves capital expenditure. 50% reduction in long-term downs potentially reduce buffer capacity by ~10%-15%: Public

Customer service value depends on three fundamentals Slide 10 29 Sept. 2021 High availability and minimal long-term downs € Lowest possible service cost per wafer Maximum good wafers per day Public    

High availability and minimal long-term downs Slide 11 29 Sept. 2021 DUV: mature platform with >97% average availability. 1%+ availability improvement still DUV possible 1%+ improvement EUV opportunity EUV: relatively immature platform with larger 7%+ opportunity of 7%+ availability improvement improvement opportunity Key improvements: • Design improvements • Software upgrades • Using technology to service our systems • Parts and tools availability • Operational improvements: site-to-site benchmarking System downtime according to standardized definition 13 weeks moving average June/ July/ August 2021 Actuals Public

Lowest possible service cost per wafer Slide 12 29 Sept. 2021 DUV EUV ~ -20% ~ -30% Current 2025 Current 2025 performance target performance target • Perfecting the machine (closed-loop feedback process to perfect the parts, tools and service actions) • Technology (e.g., diagnostics, Remote Expert Support) • Standardized processes supported by automation • Increased parts lifetime and quality • Logistics: freight, warehousing cost reduction Public    

Maximizing customers’ good wafers per day Next to minimizing system down time Slide 13 29 Sept. 2021 100% 100% 100% System downtime System downtime serving according to customer needs standardized >97% Process-specific inefficiencies definition e.g., system down to meet customer specs, layer qualification after system down, defectivity monitoring and more > 90-95% > 85-90% System uptime System uptime producing capable of producing customer wafers wafers Historical service model: New service model: Maximize scanner availability Maximize good wafers per day Public

Overview of examples driving three fundamentals Slide 14 29 Sept. 2021 € Foundational aspects Availability & Good Wafers Cost down long-term per day downs Improve system capabilities Top X continuous module / part improvements Lifecycle management & leveraging commonality between platforms Automated recovery / calibration of systems after maintenance Improved recoveries to avoid process fingerprint change after part swap Improve process capabilities Improved monitoring capabilities & leveraging machine learning towards predictive maintenance Improved diagnostics capabilities (deterministic diagnostics) Self-sufficiency of local field offices Over-the-shoulder remote support using augmented reality Inline defectivity monitoring and control strategies Scanner matching improvements Alignment mark optimization Track-delay reductions Cost reduction Freight cost reduction Inventory reduction via dynamic stocking strategies Standardized & optimized processes Excess & obsolescence reduction via improved configuration management & re-use Establish local repair centers Public

Technology innovations are improving service ASML Remote Expert Support connects experts virtually to the field Slide 15 29 Sept. 2021 • COVID-19 travel restrictions and quarantine requirements impacted fly-in support of experts to the field • Real-time data connectivity and over-the-shoulder HoloLens augmented reality enable • Faster service recovery cycle time with immediate access to factory experts • Reduced service incidents with improved preventative maintenance • Pro-actively monitoring tool health to enhance roadmap for predictive maintenance in the field Veldhoven San Diego Public

Slide 16 29 Sept. 2021 Public    

Technology innovations are improving service Using diagnostics to improve availability, reduce long-term downs & cost Slide 18 29 Sept. 2021 Reactive diagnostics Status Smart Diagnostic monitoring diagnostics action plan Machine down Data Automated monitoring to Pattern recognition to Interactive deterministic detect real-time failures identify failure modes flow to guide engineer Feedback loop Proactive diagnostics Health Health Diagnostic monitoring analytics action plan Data Machine risks Automated Fab health AI & knowledge-based Interactive deterministic monitoring to detect risks models to identify flow to guide engineer corrective actions Feedback loop Public

Improving NXT:1980Di fleet productivity at a Memory customer Slide 19 29 Sept. 2021 Average scanner output Improvement breakdown 5,300 5,300 200 5,100 5,150 350 y da 4,700 day 4,500 250 4,500 per per WafersWafers Customer Optimized Productivity Improved Productivity Customer Q1 Q2 Q3 Q4 fleet production package availability fleet after fleet Quarters after start engagement baseline settings rollout allowing program baseline higher utilization Public

Installed Base business growth Maximizing service value—High availability and minimal long-term downs—Lowest possible service cost per wafer—Maximum good wafers per day • Extending useful life of equipment through upgrades    

Types of upgrades and buying behavior Slide 21 29 Sept. 2021 Upgrades are a relatively quick and cost-effective way to improve output and process capability of lithography in the fab • Productivity • Imaging and overlay • Life-time extension Factory utilization dictates ability to install upgrades • Software upgrades provide quick improvements, always in demand • Hardware upgrades require longer downtime, in higher demand in time of lower utilization Public

System Node Enhancement Package (SNEP) Upgrade to re-use existing scanners for more advanced technology nodes Slide 22 29 Sept. 2021 SNEP brings NXT:1960 to NXT:1980 ...with the same overlay ...and a 28% in 6 weeks with field upgrade performance productivity increase 295wph +28% Non-touched parts Outer covering Type panel Replaced Parts Exposure Unit Right Left LMA UECB Machine overlay HOSE EU CABLE RH BUNDLES RH Dynamics Rema E Sensor ELEC Lens EUBUNDLES ROBOT TURRET REMA T Unicom FLG PSE FDE MMA Factory NXT:1980Di                SNEP NXT:1980Di 230wph NX XCHA gripper MASU HLPR ILLuminator LCBCR Flexray c flow ELEC IRL LIFT optics o CO2- SHB- RS ACC RTS FPPL n CU SPMR DICR OIU Cooling LoS nchuck [nm] IRIS Lens Top Micro-Environment SS encoder purging e CTSS ct PR Lens RCXU beam Illuminator io GCU LOADPORT E-box sNEXZ LS LM n SHB-E RS RSSU RECO pl Flexwave NPU EIM MMCR BF2MF ADE a IH Supplies FW exhaust DC t + Smash combiner demux e SCCB OADB AM PAL AM spacer spacer CUP Metro s DU Heat exch for WH air WTC LSPH UVLS AG AA Frame VAT WVAC XCDA1 IMCR overlay WH RA LBC Base Frame CO2 LCW heater SPM IH Beam store unit WS Airshower Measuring T ROBOTS PM-1 PM-2 unit Dedicated dockin ESCAL TIS ILIAS PARIS ESCAL TIS SPOT PARIS GH AMCR PA module LoS SS WT LoS SS WT Beam RI LEFT Carrier WH SMA handler cabinet WS BaMo LSPU unit steering M M CA CTCP CA Fab. delivery Aorta Subfab. C LASER Beam-Expander Beam LCWC UPW WVCC MDRC XCHA AERC RSRC PE fan L NXT:1960Bi NXT:1980Di+PEP RCWC Safety Beam WSRC1 WSRC2 ACC SACR SHB- Shutter steering Air Control SMA unit Cabinet RCOA LICB CHA Public

Installed Base Management Key messages Slide 23 29 Sept. 2021 Installed Base revenue is expected to grow ~12% CAGR (2020-2025) with a value-based service model plus productivity and performance upgrades As Lithography is the constraint in the fab, maximizing good wafers per day is key to optimizing fab capital asset utilization and increasing customer return on investment Customer service value depends on three fundamentals:—High availability and minimal long-term downs—Lowest possible service cost per wafer—Maximum good wafers per day Upgrades provide an efficient means of improving system output and extending the useful life of the tool for future nodes Public

Forward Looking Statements Slide 24 29 Sept. 2021 This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy, dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”, “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets, as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets, changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for, and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of this report or to conform such statements to actual results or revised expectations, except as required by law.. Public

ASML Small Talk 2021 Investor Day Virtual ASML

Exhibit 99.8

Business Model and Capital Allocation Strategy Roger Dassen Executive Vice President & Chief Financial Officer    Public Investor Day Virtual ASML Small Talk 2021 ASML

Business model and capital allocation strategy Key messages Slide 2 29 Sept. 2021 Our continued investments in technology leadership have created significant shareholder value Growth in semiconductor end markets and increasing lithography intensity on future nodes fuel demand for our products and services Based on different market scenarios, we have an opportunity to achieve an annual revenue for 2025 between approximately €24 billion and €30 billion with a gross margin for 2025 between approximately 54% and 56%. We see significant growth opportunities beyond 2025. Assuming a 1 trillion dollar semiconductor market by 2030, with litho intensity and our market share constant from 2025, we expect an annual revenue CAGR for 2020-2030 of around 11% We expect to continue to return significant amounts of cash to our shareholders through a combination of growing dividends and share buybacks Public

• Historical shareholder value creation Continuing growth Continued shareholder value creation

ASML’s technology leadership comes from strategic investments that enable cost-effective innovations for our customers Slide 4 29 Sept. 2021 Berliner Glas acquisition (0.3B€) Carl Zeiss SMT Holding 3.2 acquisition 24.9% interest 2.9 (1.0B€) 1.0 Cymer acquisition HMI acquisition 2.2 0.9 (3.1B€) (2.8B€) € B 1.6 0.6 In 1.4 1.4 1.4 0.4 1.1 0.4 0.4 0.3 0.9 2.2 0.8 0.2 2.0 0.7 0.3 1.6 0.2 1.3 0.1 0.9 1.1 1.1 1.1 0.5 0.6 0.6 2010 2011 2012 2013 2014 2015 2016 2017* 2018 2019 2020 R&D Capex * ASML contribution Zeiss SMT CapEx included as of 2017 Public

ASML’s EPS has grown at a CAGR of 14% driven by system and installed base revenue with improved margins Slide 5 29 Sept. 2021 EPS/ GM/ Revenue • Systems revenue grew at a 10% CAGR since 2010 • Installed Base Management* grew at a 20% CAGR since 2010 driven by upgrades and service of growing installed base • Gross Margin amount improved at a 13% CAGR since 2010, reflecting the strength of our DUV and Applications business and progress in EUV profitability • EPS grew at 14% CAGR since 2010 driven by profitability and share buyback * Installed Base Management equals our service and field upgrades sales Public    

ASML created significant shareholder value over the past 10 years Slide 6 29 Sept. 2021 Total Shareholder Return ASML (Nasdaq) Total Shareholder Return annualized compounded TSR 29% versus Nasdaq at 18% Source: Bloomberg (Total Shareholder Return: index = 2010) Total Shareholder Return (TSR) = shareprice increase + dividend pay-out Public    1,600 1,400 1,200 1,000 800 600 400 200 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 ASML (Nasdaq) NASDAQ Index S&P 500 Index SOX Index AEX Index

Historical shareholder value creation • Continuing growth Continued shareholder value creation    

Model scenarios Process Slide 8 29 Sept. 2021 End markets Start with end markets Convert to wafer demand: 2025 Wafer demand Low—High scenarios scenarios:—High Translate to ww units, convert Litho spend—Low to ASML share Installed Base Estimate growth of our business Installed Base business Public

Semi end markets expected to grow 7% longer-term Slide 9 29 Sept. 2021 Smartphone (B$) Consumer electronics (B$) Personal computing (B$) +6.7% +7.8% +2.6% 161 155 155 160 69 67 70 120 119 113 144 64 66 109 110 115 102 100 116 48 93 86 87 108 106 36 43 48 43 83 78 76 35 15 16 17 18 19 20 21 22 23 24 25 15 16 17 18 19 20 21 22 23 24 25 15 16 17 18 19 20 21 22 23 24 25 Wired & wireless infrastructure (B$) Servers, datacenters & storage (B$) Total Semiconductor, B$ +8.0% Forecast +5.9% 112 +7.4% 51 110 47 47 49 92 97 99 44 81 667 37 36 38 76 32 30 31 63 61 627 626 42 42 571 605 476 466 15 16 17 18 19 20 21 22 23 24 25 15 16 17 18 19 20 21 22 23 24 25 422 422 Automotive (B$) Industrial electronics (B$) 335 341 +10.2% +15.7% 80 81 75 73 65 67 58 64 58 42 41 50 46 52 50 50 34 39 39 37 35 30 CAGR 15 16 17 18 19 20 21 22 23 24 25 15 16 17 18 19 20 21 22 23 24 25 2020-2025 15 16 17 18 19 20 21 22 23 24 25 Source: ’19-’25: Gartner 2Q21 forecast (Jun30, 2021) Public    

Translating to growth of wafer demand in all segments Slide 10 29 Sept. 2021 2015 2020 2025 CAGR 1..7 1.1 +9.9% Logic & MPU 0.5 (£ 28 nm) 1.8 1.4 1.2 +5.2% DRAM 2.1 1.5 1.6 +5.7% NAND million wafer starts/month PCs and laptops Smartphones and tablets Servers Automotive Consumer incl. wearables Other Source: Gartner device units 2017-2022; ASML model extrapolated through 2025 Public

Lithography spend increasing on future nodes Slide 11 29 Sept. 2021 Logic / MPU DRAM NAND Performance memory Storage memory 45K wafers/month 100K wafers/month 120K wafers/month 1 >20% NoN1 >10% NoN1 ~30% NoN High NA EUV ArFi Dry 1 NoN: Node on Node Public

Installed Base Management*: growing installed base provides opportunity for growth in service and upgrades Slide 12 29 Sept. 2021 Growth drivers: Installed Base Management: Services and upgrades Revenues B€ • Growing installed base 8 7 • Service: move to value- ) € ~12% CAGR based services(B 6 nue reve 5 4 • Upgrades: design for Base ~13% CAGR extendibility, enabling 3 performance upgrades Installed 2 1 0 2015 2020 2025 * Installed Base Management equals our service and field upgrades sales Public

Model assumptions 2025 Slide 13 29 Sept. 2021 Logic / MPU Performance memory Storage memory Market share assumptions: EUV 100%, ArFi 90%, Dry 65% • EUV High-NA high volume from 2025 • EUV High-NA from D0a onwards • Storage class memory remains General • 2 year cadence a niche • 3D NAND: stack of stacks • Reference 16/14nm, 315 kwspm1 • Bit growth: • Bit growth: Market • Node on node (reduction): Low: 15% Low: 25% (Low—High) Low: -15% High: 25% High: 45% High:                0% • 20-30 EUV exposures • 60-70% of wafer capacity EUV • First EUV High-NA node ~ 4-9 converted to nodes with up to 8 exposures exposures of EUV 1 kwspm: 1000 wafer starts per month Public

Key challenges* we face in our industry Slide 14 29 Sept. 2021 Geo(political) landscape General ASML • Technological sovereignty • End-market growth dynamic • Managing execution of leading to new fabs in more • War for talent technology roadmap regions • Increasing focus on • Managing ramp in production • Export controls sustainability • Managing growth • IP protection Customers Suppliers Competitors • Limited number of • Growing complexity supply • Immersion customers chain • Dry • Sales concentrated among • Increasing investment • Metrology + Inspection few large customers requirements for suppliers • Managing lead times In a booming chip market, ASML’s challenge is to remain competitive in DUV, ramp 0.33 EUV, execute our 0.55 EUV (High-NA) program and expand the Holistic Litho program opportunities in order to create value for all our stakeholders, while navigating the geopolitical landscape. *For full list of risk factors, see Annual Report 2020 Public

Our updated model goes beyond our high-market scenario from 2018 Slide 15 29 Sept. 2021 ASML modeled Sales in 2025    (in B€) 2018 high market scenario Market demand EUV insertion based on mid EUV insertion based on moderate market Worldwide units Sales Worldwide units Sales High-NA                9 Systems 17.9 High-NA                7 Systems 13.4 EUV                55 Installed Base 6.4 EUV                43 Installed Base 5.9 High ArFi 60 Management ArFi 40 Management High demand Dry                200 Dry                150 insertion Total                324 Total 24.3 Total                240 Total 19.3 Worldwide units Sales Worldwide units Sales High-NA                5 Systems 10.2 High-NA                3 Systems 12.7 EUV                32 Installed Base 4.8 EUV                45 Installed Base 5.8 Low ArFi 35 Management ArFi 40 Management Low demand Dry                140 Dry                150 insertion Total                212 Total 15.0 Total                238 Total 18.5 Public

Our simulation model 2025 supports total sales between                ~24 B€ (Low market) – ~30 B€ (High market) Slide 16 29 Sept. 2021 ASML modeled sales in 2025    (in B€) Worldwide litho units Sales High-NA                5 Systems (Litho and M&I) 23.0 EUV                70 Installed Base Management 7.0 High market ArFi 87 Dry                290 Total                452 Total 30.0 Worldwide litho units Sales High-NA                5 Systems (Litho and M&I) 18.0 EUV                48 Installed Base Management 6.0 Low market ArFi 70 Dry                190 Total                313 Total 24.0 Note : 70x EUV units in 2025 (High market) equals ~115x NXE:3400C units for wafer capacity equivalent; M&I : Metrology and Inspection Public

Higher sales across product portfolio translates to increase in 2025 modeled scenario Slide 17 29 Sept. 2021 ASML 2025 modeled sales (mid point of range) € ) (B sales Modeled *Non EUV = DUV, Metrology and Inspection **IBM = Installed Base Management Public

ASML updated financial model Slide 18 29 Sept. 2021 2020 2025 2025 (Actuals) (CMD 2018 Ranges) (Low—High market) Total sales 14.0B€ ~15—24B€ ~24.0—30.0B€ Installed base 3.7B€ ~5—6B€ ~6.0—7.0B€ Management System sales 10.3B€ ~10—18B€ ~18.0—23.0B€ Gross margin 48.6% >>50% ~54—56% R&D 16% ~13% ~3.4—3.7B€ SG&A 4% ~4% ~1.0B€ CapEx 7% ~3% ~1.0B€ Cash Conversion Cycle 228 days <200 days <200 days Effective Tax Rate* 14% ~14% ~16% * Based on 2021 tax legislation Public

Market opportunities support another 10 years of growth Slide 19 29 Sept. 2021 Drivers 2020 2025 2030 CAGR Systems: New and existing technology nodes Litho, in all segments will continue to be the ~11%* Metrology & main driver for our system revenue for Inspection litho and metrology & inspection ~10.3B€ Installed Growing installed base and Base move to value-based service Management increases our opportunity ~11% ~3.7B€ Source: VLSI Research, with ASML analysis; Installed Base Management : ASML service and field upgrades sales; * Assumes litho intensity (litho % of WFE) and litho market share in 2030 similar to 2025; * Systems revenue CAGR, includes ASML Metrology & Inspection system revenue CAGR 2020-2030 ~15% Public

Historical shareholder value creation Continuing growth • Continued shareholder value creation    

ASML’s capital allocation policy Slide 21 29 Sept. 2021 Focused investment in our business Excess cash distribution through R&D, CapEx Combination of growing dividends and share Berliner Glas buybacks acquisition (0.3B€)* Carl Zeiss SMT Holding acquisition 24.9% interest 16.00 (1.0B€)* 14.0 14.00 HMI acquisition 3.2 11.7 12.00 (2.8B€) 2.9 5.4 Cymer acquisition 1.0 10.0 (3.1B€) 10.00 2.2 4.3 0.9 € 8.2 B 3.0 € 7.2 8.00 Cumulative 1.6 0.6 In dividend B 6.4 2.4 1.4 1.4 1.4 Capex 1.9 In 5.5 6.00 0.3 1.4 Cumulative 1.1 0.3 R&D 4.5 1.1 0.4 0.4 4.0 share 0.9 2.2 0.9 8.6 4.00 0.8 0.2 2.0 3.3 0.6 7.4 buybacks 0.7 2.4 7.0 0.3 1.6 0.5 5.8 0.2 1.3 4.9 5.3 0.1 1.1 1.1 1.1 0.3 4.4 2.00 0.9 3.4 3.7 0.6 0.6 2.8 0.5 2.1 0.00 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 Maintain a strong and flexible balance sheet * ASML contribution for Zeiss SMT capex included as of 2018 Public

Business model and capital allocation strategy Key messages Slide 22 29 Sept. 2021 Our continued investments in technology leadership have created significant shareholder value Growth in semiconductor end markets and increasing lithography intensity on future nodes fuel demand for our products and services Based on different market scenarios, we have an opportunity to achieve an annual revenue for 2025 between approximately €24 billion and €30 billion with a gross margin for 2025 between approximately 54% and 56%. We see significant growth opportunities beyond 2025. Assuming a 1 trillion dollar semiconductor market by 2030, with litho intensity and our market share constant from 2025, we expect an annual revenue CAGR for 2020-2030 of around 11% We expect to continue to return significant amounts of cash to our shareholders through a combination of growing dividends and share buybacks Public

Forward Looking Statements Slide 23 29 Sept. 2021 This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy, dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”, “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets, as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets, changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for, and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of this report or to conform such statements to actual results or revised expectations, except as required by law. Public

Slide 24 29 Sept. 2021ASML Small Talk 2021 ASML Investor Day Virtual

Exhibit 99.9

Closing remarks Peter Wennink President and Chief Executive Officer

Investor Day summary and key messages (1/2) Slide 2 29 Sept. 2021 • Global megatrends in the electronics industry, supported by a highly profitable and fiercely innovative ecosystem, are expected to continue to fuel growth across the semiconductor market • Growth in semiconductor end markets and increasing lithography intensity are driving demand for our products and services • ASML’s comprehensive product portfolio is aligned to our customers’ roadmaps, delivering cost effective solutions in support of all applications from leading edge to mature nodes • Based on different market scenarios, we have an opportunity to reach annual revenue in 2025 between approximately €24 billion and €30 billion, with a gross margin in 2025 between approximately 54% and 56% • We see significant growth opportunities beyond 2025. We expect our systems (lithography, metrology and inspection) and Installed Base Management (service and field upgrades sales) to provide an annual revenue growth rate of around 11% for the period 2020-2030, based on third party research and our assumptions    

Investor Day summary and key messages (2/2) Slide 3 29 Sept. 2021 • ASML and its supply chain partners are actively adding and improving capacity to meet this future customer demand • Our ESG Sustainability strategy builds on achieved performance improvements and details how we plan to contribute to a digital, sustainable future • Our continued investments in technology leadership have created significant shareholder value • We expect to continue to return significant amounts of cash to our shareholders through a combination of growing dividends and share buybacks    

Forward Looking Statements Slide 4 29 Sept. 2021 This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy, dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”, “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets, as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets, changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for, and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of this report or to conform such statements to actual results or revised expectations, except as required by law. Public

ASML Small Talk 2021 Investor Day Virtual ASML