Verkor Launches Industry's First TurboQuant LLM Inference Accelerator Silicon IP

Highlights:

• VerTQ is an accelerator chip that implements Google's TurboQuant algorithm which reduces KV cache memory usage of Large Language Models by a factor of 4.3x while maintaining or enhancing performance.
• VerTQ was built 100% autonomously by Conductor 2.0, Verkor's second generation agentic AI platform in conjunction with standard EDA tools.
• VerTQ's scalable architecture supports 1-32 attention decoders. Mapped to a Xilinx XCVU29P-3 FPGA running at 125 MHz, VerTQ consumes 500,619 LUTs, 247,022 FF, 748 DSP48E2, 4 RAMB36 and 9 RAMB18 for a single attention decoder. If integrated into an XPU silicon, it significantly boosts inference token rates with minimal cost in area and power.

LOS ALTOS, Calif., May 19, 2026 /PRNewswire/ -- Verkor, Inc., an Enterprise Agentic AI startup, unveiled Industry's first TurboQuant silicon IP, VerTQ.

VerTQ is an accelerator IP that implements Google's TurboQuant algorithm (https://arxiv.org/abs/2504.19874) which reduces KV cache memory usage of Large Language Models by a factor of 4.3x. This algorithm directly enables LLM inference applications to use less memory (which is currently in short supply) and to run faster as it saves precious memory bandwidth. Google announced the TurboQuant (TQ) algorithm (in mathematical form) on March 24, 2026; as of publication date there is not, to the best of our knowledge, any hardware implementation of TQ. Google's TQ announcement had a direct effect on the stock prices of leading memory chip manufacturers. VerTQ handles the compression of KV data and, additionally, accelerates computationally burdensome Attention algorithm by performing Flash Attention operations on-chip, including online SoftMax. These operations are performed without decompressing KV-cache data, which further saves memory bandwidth. VerTQ is specifically intended for edge AI applications, such as automobiles, drones, and robots, where compact size, power/compute efficiency and low-cost are key. Conductor 2.0 built VerTQ in about 80 hours from algorithm to fully function and timing-verified FPGA implementation.

The customer deliverable package for VerTQ includes product specification, microarchitecture specification, test plan, verification IP, unit and system level testbenches, hierarchical RTL with comments, FPGA netlist and downloadable image, and design documentation. It is available now.

"Conductor 2.0 compresses the chip development cycle from years to weeks. We're constantly enhancing Conductor, running it on ever-larger chip designs, to deliver complex silicon IPs from impactful algorithms." said Suresh Krishna, CEO of Verkor.

For more information on VerTQ and Conductor 2.0, please find the technical paper at https://arxiv.org/abs/2605.05170.

For inquiry about VerTQ and other IPs generated by Conductor 2.0, please contact David Chin at [email protected].

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SOURCE Verkor Inc.