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SEALSQ's QS7001 chip delivers quantum-resistant security compliance

November 25, 2025 9:02 AM EST

SEALSQ Corp (NASDAQ: LAES) announced that its QS7001 Quantum Shield secure element provides CNSA 2.0 compliance through hardware-embedded post-quantum cryptography. The chip is currently in volume production and shipping to customers worldwide.

The QS7001 integrates NIST-standardized algorithms including Module-Lattice-Based Key Encapsulation Mechanism (ML-KEM) and Module-Lattice-Based Digital Signature Algorithm (ML-DSA) directly into hardware. The secure element runs on a 32-bit Secured RISC-V Architecture Microcontroller and supports hybrid cryptography models that combine classical and post-quantum schemes.

The chip has achieved Common Criteria EAL5+ and FIPS 140-3 certifications. SEALSQ states the QS7001 supports secure boot mechanisms and firmware updates configurable for CNSA 1.0, CNSA 2.0, or mixed-mode deployments for IoT, industrial, and defense applications.

SEALSQ launched a U.S.-based Post-Quantum Root of Trust service on November 21, 2025, which generates CNSA 2.0-compliant certificates and device identities. The service operates through secure personalization centers in Switzerland, France, Spain, with facilities planned for India and the U.S.

"With the QS7001 already deployed in production systems worldwide, customers can achieve full CNSA 2.0 compliance today," said Carlos Moreira, Founder and CEO of SEALSQ.

The company plans to release QVault TPM variants in the first half of 2026 to extend quantum-resistant capabilities to trusted platform modules ahead of the 2027 U.S. government deadline for quantum-resistant cryptography. SEALSQ reports its solutions secure over 1.75 billion devices worldwide through partnerships with foundries including UMC.

Production samples and volume orders of the QS7001 are available, with comprehensive SDKs and evaluation kits accessible through the company's developer portal.



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