IBM (NYSE: IBM) and Siemens announced a research collaboration aimed at advancing IBM's nanostack architecture, a three-dimensional, nanosheet-based transistor design IBM unveiled earlier in 2026.

The nanostack architecture vertically stacks and staggers transistors, allowing for nearly 100 billion transistors in a space the size of a fingernail at its current 7 angstrom node. The design also permits different material combinations within each stacked layer to optimize performance and power efficiency independently per transistor.

IBM said it demonstrated the viability of the nanostack architecture earlier this year. The new collaboration with Siemens is intended to advance the technology toward manufacturing and production at scale.

Under the agreement, the two companies will work to develop design, simulation, and lithography techniques for current and future nanostack generations beyond the 7 angstrom node. This includes building advanced virtual models of nanostack to assess performance, optimize designs, and identify fabrication challenges before physical chips are produced.

Siemens will contribute expertise in electronic design automation, process simulation, lithography optimization, and advanced manufacturing software, according to the press release.

"Nanostack is a scalable transistor platform designed to shift device scaling from 2D to 3D, representing a new paradigm for the semiconductor industry," said Huiming Bu, Vice President of Silicon Technology R&D at IBM.

Ankur Gupta, Executive Vice President of EDA IC Portfolio at Siemens, said the collaboration aims to "address physical limitations early and accelerate the development of these complex architectures."