Cadence Design Systems Inc. (NASDAQ: CDNS) announced the launch of what it calls the industry's first fully autonomous virtual engineer for semiconductor design at Computex 2026. The ChipStack AI Super Agent operates at Level-5 autonomy, executing chip design and verification workflows independently.

The system is built on Cadence's electronic design automation portfolio using NVIDIA Nemotron models and operates within NVIDIA OpenShell runtime environment. The technology enables engineers to run dynamic simulations in automated workflows using Cadence Xcelium Logic Simulation and Jasper Formal Verification tools.

According to the company, NVIDIA engineers using the system have reduced typical five-week verification loops to less than one day, representing what Cadence claims is a 40-fold acceleration in RTL validation cycles. The system processes hundreds of dynamic simulations automatically rather than requiring step-by-step prompts.

"With the ChipStack AI Super Agent, we're taking the next step—moving from AI that assists engineers to autonomous virtual engineers that can implement real design and verification work," said Paul Cunningham, senior vice president and general manager of the System Verification Group at Cadence.

The autonomous agent evaluates intermediate results and determines next actions across tasks including specification understanding, RTL generation, verification planning, formal analysis, simulation and design convergence. Engineers supervise outcomes and provide guidance rather than executing individual tasks.

The system operates within NVIDIA OpenShell, which provides a sandboxed environment with governance controls and IP protection through policy controls and managed access to tools and design data.

Cadence acquired ChipStack in November 2025 and launched its first product in February 2026. The Level-5 autonomous capabilities are expected to be available to early-access customers in the second half of 2026.