Cadence Design Systems (NASDAQ: CDNS) announced an expanded collaboration with Taiwan Semiconductor Manufacturing Company to accelerate AI-driven semiconductor innovation. The partnership will deliver design infrastructure and certified flows for AI silicon on TSMC's N3, N2, A16 and A14 process technologies.

The collaboration aims to help customers reduce design iterations and improve correlation for advanced AI and high-performance computing designs. Cadence stated that customer momentum shows many companies are actively designing on TSMC's 3nm or 2nm technologies.

"AI silicon innovation at advanced nodes demands a signoff-ready approach that spans the full design cycle and scales from SoCs to chiplet and 3D-IC architectures," said Chin-Chi Teng, senior vice president and general manager at Cadence.

Cadence is providing IP portfolio for TSMC N2P, including DDR5 12.8G MRDIMM, PCIe 6.0, LPDDR6/5X 14.4G and HBM4E 16G. The company's Artisan foundation IP portfolio is in production designs using TSMC N3 process technologies.

The partnership includes certified design flows that scale from advanced-node systems-on-chips to chiplet and 3D-IC designs. Tools include the Innovus Implementation System, Virtuoso Studio, Spectre Simulation Platform, and various signoff technologies certified for TSMC N2 and A16 processes.

Cadence is developing what it calls "agent-ready" design flows that integrate AI to enable goal-driven optimization. The company stated this approach shifts electronic design automation from tool-by-tool workflows to goal-driven execution.

NVIDIA's Tim Costa commented on the collaboration, stating that increasing scale and complexity of AI silicon require integrated accelerated computing and AI at every stage of chip design.

Several customers provided statements supporting the partnership, including Arm's Eddie Ramirez and Positron's Thomas Sohmers, who noted the importance of ecosystem collaboration for AI and HPC deployments.