Synopsys Inc. (NASDAQ: SNPS) announced expanded collaboration with Taiwan Semiconductor Manufacturing Co. on chip design tools and intellectual property for artificial intelligence systems across TSMC's advanced manufacturing processes.

The partnership includes development of AI-powered electronic design automation flows and semiconductor IP solutions for TSMC's 3-nanometer and 2-nanometer process technologies, as well as A16 and A14 nodes. Synopsys reported successful silicon validation of M-PHY v6.0 IP on TSMC's N2P process and tape-out of 64G UCIe IP.

The companies are working on agentic run assistance in Synopsys Fusion Compiler for TSMC's A14 process using NanoFlex Pro architecture. Synopsys' 3DIC Compiler platform provides design capabilities for TSMC's CoWoS technology at 5.5x reticle interposer sizes for multi-die designs.

Synopsys expanded its IP portfolio with 224G solutions for co-packaged optical Ethernet and UALink connectivity. The company achieved first-silicon milestones on TSMC's N5, N3P, and N2P processes for various IP including PCIe 7.0, HBM4, DDR5 MRDIMM Gen2, and LPDDR6/5X/5.

The collaboration extends multiphysics design enablement for COUPE to support co-packaged optics for datacenter connectivity. Power integrity platforms span digital and analog domains across TSMC's advanced nodes.

"TSMC's most advanced process and packaging technologies are opening new frontiers for performance, bandwidth, and energy efficiency in AI and autonomous systems," said Michael Buehler-Garcia, Senior Vice President at Synopsys.

Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC, said the collaboration aims to meet growing demands of AI and high-performance computing applications.