Taiwan Semiconductor Manufacturing Co. (NYSE: TSM) announced its A13 process technology at the company's 2026 North America Technology Symposium in Santa Clara, California. The A13 process represents a direct shrink of TSMC's A14 node and is scheduled to enter production in 2029.

The A13 technology provides 6% area savings compared to the A14 process while maintaining full backward compatibility with A14 design rules. TSMC stated the technology uses nanosheet transistor architecture and targets artificial intelligence, high-performance computing, and mobile applications.

TSMC also introduced several other technologies at the symposium. The company unveiled A12, an A14 platform enhancement featuring Super Power Rail technology for backside power delivery, also scheduled for 2029 production. Additionally, TSMC announced N2U, which offers 3-4% speed gains or 8-10% power reduction compared to N2P, with production planned for 2028.

For advanced packaging, TSMC expanded its Chip on Wafer on Substrate (CoWoS) technology. The company is producing 5.5-reticle size CoWoS and planning a 14-reticle size version capable of integrating approximately 10 large compute dies and 20 HBM stacks for 2028 production.

In automotive applications, TSMC introduced N2A, described as the first automotive-grade process technology with nanosheet transistors. N2A provides 15-20% speed gain at the same power compared to N3A and is scheduled to complete AEC-Q100 qualification in 2028.

The company also announced N16HV, a high voltage process for display driver applications entering production in 2026. For smartphone display drivers, N16HV increases gate density by 41% and reduces power by 35% compared to TSMC's N28HV process.

"TSMC's advanced process technologies lead the industry in density, performance and power efficiency," said Chairman and CEO C.C. Wei, according to the company's press release.