Keysight Technologies Inc. (NYSE: KEYS) introduced the Functional Interconnect Test Solutions (FITS) portfolio and its first product, FITS-8CH, designed for digital-layer bit error ratio and forward error correction performance validation of high-speed optical and copper interconnects.

The FITS-8CH system addresses testing requirements for PAM4 electrical lanes operating at 53 Gb/s, 106 Gb/s, and 212 Gb/s speeds, which support 400GE, 800GE, and 1.6T Ethernet network architectures used in AI data centers and network equipment.

The system provides simultaneous, bi-directional real-time testing across eight transmit and eight receive channels. It features two channel groups - high-drive outputs and chip-to-module interfaces - to support different electrical fixtures and interconnect configurations.

FITS-8CH includes automated lane tuning that adjusts transmit tap settings and optimizes PAM4 signal output for each lane. The system generates IEEE P802.3dj-compliant signals and can identify manufacturing issues such as mechanical misalignment and thermal failures during testing processes.

"With FITS-8CH, Keysight provides the digital-layer error performance analysis we need to verify 1.6T AEC BER-per-lane requirements under realistic operating conditions," said Kenji Liao, High-Speed Interconnect PM Director at UDE Corporation.

The solution integrates with Keysight's existing physical layer test solutions and supports validation throughout design, development, and manufacturing stages. Keysight plans to showcase the FITS portfolio at the OFC Conference in Los Angeles from March 17-19, 2026.

This announcement expands Keysight's testing capabilities beyond physical-layer validation to system-level error performance testing for high-speed interconnects used in network infrastructure and data center applications.